Once again Im here to disturb you!!
In this circuit I use R1 as 120Ω and C1 as 22nF. My out put is about around 4 KHz (input exactly 1024Hz) but not stable output. now I want that if im give input around 1024 Hz, then my output should be 65553 Hz or 65.536KHz. what should I do now???
I know that you have better idea than this, if mine is not sufficient enough for this purpose, then plz enlighten me with other method. And remeber I dont know the microcontrller!
have also seen the 4011 frequency doubler but that was complicated.
So you are saying that you need more than frequency doubling but multiplying that frequency by a constant like 64? You have to use a different approach.
The circuit you are linked to may not be super stable either. That's because it is using ordinary logic interfaced directly to capacitors on the input. That calls for a Schmitt Trigger gate on the input of the XOR gate or similar. Without that you may experience multiple pulses where you only want one.
So you are saying that you need more than frequency doubling but multiplying that frequency by a constant like 64? You have to use a different approach.
The circuit you are linked to may not be super stable either. That's because it is using ordinary logic interfaced directly to capacitors on the input. That calls for a Schmitt Trigger gate on the input of the XOR gate or similar. Without that you may experience multiple pulses where you only want one.
yes, the output is not stable. what can I do please suggest me....I'm waiting for your replay.
and please suggest me without microcontroller, because I don't know the subject...
Now look at the Functional Diagram Fig1, if you put a divide by 64 circuit ( a six stage binary divider) in the block marked "/N", and make the VCO run at 64kHz, and use your 1024hz signal as the reference frequency at Sig In you will be in with a chance of success.
Now look at the Functional Diagram Fig1, if you put a divide by 64 circuit ( a six stage binary divider) in the block marked "/N", and make the VCO run at 64kHz, and use your 1024hz signal as the reference frequency at Sig In you will be in with a chance of success.
Yes, a phase locked loop (PLL). Isnt that the data sheet Jim linked to?
That allows you to input a low frequency and get out a higher frequency. It's a little complicated, but that's the way it is usually done.
The data sheet should tell you how to do it, but if not you can look for circuits on the web that will show some hookups.
Yes, a phase locked loop (PLL). Isnt that the data sheet Jim linked to?
That allows you to input a low frequency and get out a higher frequency. It's a little complicated, but that's the way it is usually done.
The data sheet should tell you how to do it, but if not you can look for circuits on the web that will show some hookups.
that's a very helpful circuit. but i have one question and that is if the Input frequency is 63Hz, then the output will be 63KHz ??????
but I need this>>> If input frequency is 1HZ, output will be 128Hz....
so where should I change in that CIRCUIT?????
A PLL will only multiply a frequency by what you can divide the output down to so it equals the reference frequency. So if you want to multiply by say 19, then you are in a world of hurt unless you start using a proper frequency synthesiser which are lots of components or need a CPU to program.
There used to be a super chip by Motorola that could do this. Not sure if it's still available but look here: http://www.datasheetcatalog.org/datasheet/motorola/MC145151-2.pdf
I used it many years ago with a /63/64 Plessey Semiconductor chip to produce a local osc for a receiver.
I need it to multiply with 128. Input frequency X 128 = output. if the input frequency is 2 hz, then Output have to 256hz.
so is it possible to multiply with 128????
I need it to multiply with 128. Input frequency X 128 = output. if the input frequency is 2 hz, then Output have to 256hz.
so is it possible to multiply with 128????
Yes, but see my previous posting about stability. During an off period, the oscillator on a PLL free runs and is "pulled back" by the reference. It happens at all frequencies but is more noticable at lower reference frequencies.
Yes, but see my previous posting about stability. During an off period, the oscillator on a PLL free runs and is "pulled back" by the reference. It happens at all frequencies but is more noticable at lower reference frequencies.
that's a very helpful circuit. but i have one question and that is if the Input frequency is 63Hz, then the output will be 63KHz ??????
but I need this>>> If input frequency is 1HZ, output will be 128Hz....
so where should I change in that CIRCUIT?????
If you need an output that is 128 times the input frequency, that's no problem. Just use one 7 or 8 bit counter instead of all those counters shown in the diagram i provided.
You may also need to change a resistor and capacitor to get the frequency range you need. Check out the data sheet and see what you think.