So I designed a simple buck smps and I was wondering if anybody can point me in the right direction on what is happening in my simulations when I add a compensation network to my feedback loop.
Here is the simplified schematic of what I am simulating -
**broken link removed**
The issue of I am having is when the error amplifier transistions from low to high, the output node is so sharp and the cap is so big that the output couples into the feedback node and causes the error amplifier output to stay high for many more cycles than it should, causing lots of ripple on my output. Here is the spice simulation output of what I am talking about:
**broken link removed**
There are no parasitics (other than esr's for the cap and the inductor) and my opamp model is fairly ideal (which is causing the sharp edges). Is this output expected or do I need to model my circuit more accurately? Here is a schematic of the opamp model I am using:
**broken link removed**
Here is the simplified schematic of what I am simulating -
**broken link removed**
The issue of I am having is when the error amplifier transistions from low to high, the output node is so sharp and the cap is so big that the output couples into the feedback node and causes the error amplifier output to stay high for many more cycles than it should, causing lots of ripple on my output. Here is the spice simulation output of what I am talking about:
**broken link removed**
There are no parasitics (other than esr's for the cap and the inductor) and my opamp model is fairly ideal (which is causing the sharp edges). Is this output expected or do I need to model my circuit more accurately? Here is a schematic of the opamp model I am using:
**broken link removed**