Help with time domain response of buck smps

[FusionITR]

So I designed a simple buck smps and I was wondering if anybody can point me in the right direction on what is happening in my simulations when I add a compensation network to my feedback loop.

Here is the simplified schematic of what I am simulating -

**broken link removed**

The issue of I am having is when the error amplifier transistions from low to high, the output node is so sharp and the cap is so big that the output couples into the feedback node and causes the error amplifier output to stay high for many more cycles than it should, causing lots of ripple on my output. Here is the spice simulation output of what I am talking about:

**broken link removed**

There are no parasitics (other than esr's for the cap and the inductor) and my opamp model is fairly ideal (which is causing the sharp edges). Is this output expected or do I need to model my circuit more accurately? Here is a schematic of the opamp model I am using:

**broken link removed**

 

[FusionITR]

bump........

 

[OutToLunch]

first, there is no freewheeling diode - you need a diode with the anode tied to ground and cathode tied to the input of the inductor.

second, the output of the error amplifier should not be switching. the signal from the error amplifier should "wiggle" at steady state at a certain voltage level. The output of the error amplifier needs to be compared to a ramp and the output of that comparator is the pwm signal which is used to drive the control FET.

 

[FusionITR]

first, there is no freewheeling diode - you need a diode with the anode tied to ground and cathode tied to the input of the inductor.

Oops, you're right but it's in my real schematic, not in the simplified schematic that I posted earlier.

second, the output of the error amplifier should not be switching. the signal from the error amplifier should "wiggle" at steady state at a certain voltage level. The output of the error amplifier needs to be compared to a ramp and the output of that comparator is the pwm signal which is used to drive the control FET.

Yes, exactly, without the compensation the EA does "wiggle", but acording to the spreadsheet vol = 0.6 and voh is 2.4, so it would rail from those voltages without the compensation. For example, here is what the output looks like without the compensation attached:

**broken link removed**

Here is with the compensation:

**broken link removed**

I believe I know what the issue is though. According to the datasheet the error amplifier can only sink 500uA and source 75uA. In the simulation here are the currents of the caps when charging:

**broken link removed**

So basically my fake opamp is unrealistically strong (look at the 2mA spikes) and won't be charging up that cap as sharply as it does in my simulation. But I still think, at least on the sink side, that 500uA charge will be somewhat of a problem. Or maybe not, what do you think?

 

[FusionITR]

bump............

 

[OutToLunch]

what is the mysterious PWM block in your schematic? can you show either the voltage on the gate of the FET or the voltage at the input of the inductor as well?

what is the L? what is the dcr of the inductor? what is the output capacitance? what is the esr of that capacitance? What is the switching frequency? what is the input voltage? and what is the peak-to-peak voltage of the oscillator?

 

[indulis]

It would be a lot easier with current mode control...

 

[FusionITR]

what is the mysterious PWM block in your schematic? can you show either the voltage on the gate of the FET or the voltage at the input of the inductor as well?

what is the L? what is the dcr of the inductor? what is the output capacitance? what is the esr of that capacitance? What is the switching frequency? what is the input voltage? and what is the peak-to-peak voltage of the oscillator?

I have solved this issue somewhat. It was partly due to modeling and partly due to bad component selection. I am still having some issues with the negative rail that I want to solve before I ordering components and send the board out to the fab so I might post back in here with the answers do your questions and some more detailed waveforms.

 

[MrAl]

Hi,


If you do a full time domain analysis you first do the plant and then the feedback,
then combine them. It's not that easy if you have never done this before though.

Your values for the op amp section are the most important because they have the
ability to make the system fast or slow and stable or unstable. In particular,
the capacitor across the op amp (output to inverting terminal with no series R)
sometimes causes more problems if it is too large. It should be quite small and
even 0.004uf may be too large.
The exact compensation techniques for these circuits is a bit involved, and to
add to the difficulty many sites on the web have so many errors that they
do more harm than good. Even more reputable authors valuable information
does not get to the intended audience because of whomever typed the
information into the web site unfortunately.
This means we end up with trial and error for some of the components.
You can vary one C a little bit and see what the effect is, vary the next
and see what happens there, then vary the resistor. Eventually you can
come up with a technique that gets you there. You then have to carefully
test the system to make sure it wont go unstable with various loads and
inputs, and even some change of load situations and rising and falling
input voltage, etc.

If you do a full time domain analysis you can experiment with the values
in the equations and see what yields the best performance and stability,
so you dont have to change components in the real life circuit.

 

[FusionITR]

Hi,


If you do a full time domain analysis you first do the plant and then the feedback,
then combine them. It's not that easy if you have never done this before though.

Your values for the op amp section are the most important because they have the
ability to make the system fast or slow and stable or unstable. In particular,
the capacitor across the op amp (output to inverting terminal with no series R)
sometimes causes more problems if it is too large. It should be quite small and
even 0.004uf may be too large.
The exact compensation techniques for these circuits is a bit involved, and to
add to the difficulty many sites on the web have so many errors that they
do more harm than good. Even more reputable authors valuable information
does not get to the intended audience because of whomever typed the
information into the web site unfortunately.
This means we end up with trial and error for some of the components.
You can vary one C a little bit and see what the effect is, vary the next
and see what happens there, then vary the resistor. Eventually you can
come up with a technique that gets you there. You then have to carefully
test the system to make sure it wont go unstable with various loads and
inputs, and even some change of load situations and rising and falling
input voltage, etc.

If you do a full time domain analysis you can experiment with the values
in the equations and see what yields the best performance and stability,
so you dont have to change components in the real life circuit.

I know what I'm doing as far as stability and transient response goes. I'll post the bode plots later as I actually do have some questions/issues about it.

 

[MrAl]

Hi again,


If i remember right the buck is one of the easiest switchmode circuits to analyze.
I think you can linearize the entire circuit, replacing the PWM and switch with
a linear element, then you end up with the typical G/(1+G*H) linear circuit
and can easily analyze that for various things.
It's also a good idea to include inductor and capacitor ESR's in the analysis
because that often makes a difference in the stability of the switchmode circuits.
Yes, it's' more important in boost circuits but i wouldnt ignore it in the buck either.

Im also interested to see what else you have.

 

[FusionITR]

I already do include the esr's of the inductor and the cap, I'll post more info later.