Help needed with placement of ceramic capacitor for decoupling

[Zestfully4]

I'd like to solder the ceramic capacitor for decoupling across GND and VCC of U1/U3. I don't know what the best placement would be on this circuit, so help with visual markings on the photo would be helpful!

 

[Papabravo]

Solder them between pins 7 (GND) & 14 (VCC) on the two DIP (Dual Inline Packages) on the solder side of the board. Make sure the leads do not touch any other pins or traces.

 

[Diver300]

The best placement is to have the shortest total length of ground and Vcc leads, so that is the length of ground lead inside the IC (which you can't do anything about), the ground track from pin 7 to where you solder the capacitor, the ground side capacitor lead, the Vcc side capacitor lead, the Vcc track from where you solder the capacitor to pin 14 and finally the Vcc lead inside the IC (which you can't do anything about).

I can't see the layout of ground and Vcc tracks and if all the tracks take long paths, you might be best to solder the capacitors above the ICs, or directly under them as Papabravo suggests.

As an aside, to show the importance of short wire lengths, in the 1980s, Texas Instruments came out with a logic series, the 74AC11000 series, that had 2 or more ground pins, and two or more Vcc pins, in the middle of the sides of the IC, to minimise the length of the wires to the decoupling capacitors. https://www.ti.com/lit/ds/symlink/74ac11000.pdf

 

[Tony Stewart]

The CMOS is very low current, static and does not generate much noise, but the analog IC might draw more since it drives a piezo wafer which still might be high impedance (1k ohm). I would consider a 100uF or a low ESR 10 uF. or 1uF Ceramic. Although 0.1 uF ceramic might be OK.