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One of the main advantages that CMOS technology, which makes it the most commonly-used technology for digital circuits today is the fact that it enables chips that are small in size to have features like high operating speeds and efficient usage of energy. Besides, they have very low static power supply drain most of the time. Only when the transistors are switching between the two states (on and off) do you find a significant level of power drain. Besides, devices using CMOS technology also have a high degree of noise immunity.
what should be good characteristic for cmos circuit
1)It should be dissipate less power
2)It should have zero propagation dealy
3)should have noise immunity
4)rise time and fall time should be less
does anyone know another specification ?
how to decide width and length for nmos and pmos for following parameter
1)It should be dissipate less power
2)should have noise immunity
3)rise time and fall time should be less