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Frequency-to-Voltage Converter Stability

danigund

New Member
I am trying to understand the behaviours I am seeing when using an AD652 in the FVC mode (shown below).
1650514020015.png

(https://www.analog.com/media/en/technical-documentation/data-sheets/ad652.pdf)

I conducted a series of measurements of the output voltage (Vout) across a wide range of input frequencies (each of which was held constant for the duration of the measurement) and found that Vout experienced instabilities (fluctuating periodically) at particular frequencies that coincided with multiples of the clock frequency (2.5MHz). I'll attach my graphs below.

I have set up an LTSpice simulation but am having difficulty reproducing the circuit.
Screen Shot 2022-04-21 at 6.35.10 pm.png


I'd appreciate any help in fixing my simulation and understanding:
1. Why the output voltages follow the linear ramping pattern
  • Is this due to sampling and aliasing effects (particularly since it coincides with the clock frequency)?
2. Why the residual linearity instabilities are greater on the negative slopes
  • Could this be related to propagation delays in the digital circuit?



The following graph shows the residuals associated with the linearity of the positive and negative slopes. The residuals of the negative slopes are usually 3 orders of magnitude greater than those of the positive slopes:
1650515775732.png

This is an additional graph I made, showing the relationship of the input frequencies relative to the clock frequency (2.5MHz):

enter image description here
 
Last edited:

eTech

Well-Known Member
I am trying to understand the behaviours I am seeing when using an AD652 in the FVC mode (shown below).
View attachment 136716
(https://www.analog.com/media/en/technical-documentation/data-sheets/ad652.pdf)

I conducted a series of measurements of the output voltage (Vout) across a wide range of input frequencies (each of which was held constant for the duration of the measurement) and found that Vout experienced instabilities (fluctuating periodically) at particular frequencies that coincided with multiples of the clock frequency (2.5MHz). I'll attach my graphs below.

I have set up an LTSpice simulation but am having difficulty reproducing the circuit.
View attachment 136721

I'd appreciate any help in fixing my simulation and understanding what components of the circuit give rise to the instabilities in the Vout - Fin graphs.



The following graph shows the residuals associated with the linearity of the positive and negative slopes. The residuals of the negative slopes are usually 3 orders of magnitude greater than those of the positive slopes:
View attachment 136717
This is an additional graph I made, showing the relationship of the input frequencies relative to the clock frequency (25MHz):

enter image description here

Post your LTspice .asc file.
 

eTech

Well-Known Member
Hi

I've made some corrections to your schematic.

1. Remove the "com" connections on all the "A" logic devices. They are not needed.
2. When pins on "A" devices are not used, leave them disconnected and they will be ignored. This wouldn't be done on real digital devices but the "A" devices work this way.
3. I've added a set of common parameters for all "A" logic devices and added the params to all logic devices.
4. tau (instead of trise/tfall), along with tripdt, parameters are better to use for convergence purposes and provide smoother logic transitions.
5. I changed the "Latch" gates to a D-FF device so the timing operation reflects the waveforms shown on the datasheet.

I think the rest of the changes are self explanatory.

Try adjusting your circuit with these changes incorporated.

1650609979447.png


File attached.
 

Attachments

  • FVC-modified.zip
    2 KB · Views: 65

danigund

New Member
Thank you for that!!

One thing I am unsure of is why the output voltage bounds are now extended up to 15V. All my measurements of the circuit in the lab have given rise to output voltages between ~4.5 - 10V. Is this because of the voltage sources connected to the op amp?
 

eTech

Well-Known Member
Thank you for that!!

One thing I am unsure of is why the output voltage bounds are now extended up to 15V. All my measurements of the circuit in the lab have given rise to output voltages between ~4.5 - 10V. Is this because of the voltage sources connected to the op amp?
Which voltage sources? The +/-15v supplies? I didn't think you were finished modeling the chip. The datasheet says the output range can be from -1 to +Vs-4v (Vs=+/-15v ). So that equates to -1 to +11v and will depend on supply voltages (Vs).

I'm not very familar with the inner workings of this chip. The opamp internal supply might be +/-Vs, or maybe even asymmetric supply voltages, but other devices (like digital) might be driven by an internally regulated voltage. I thought that might where the 4.8v came from.
 

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