Continue to Site

Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

Register Log in
  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

FPGA

Status
Not open for further replies.
eddy_eclectic

eddy_eclectic

New Member
:idea: Here There is a Project Designed whit ALTERA CPLD
:arrow: The project is a Clock
:arrow: Whole the necessary files same as GDF-VHD files are exist in the FPGA_Clock.zip file and there are some informations to help you in the PDF_FPGA_Clock.zip file.
:wink: enjoy that
 

Attachments

  • fpga_clock.zip
    491.7 KB · Views: 385
  • pdf_fpga_clock_198.zip
    266 KB · Views: 468
  • install_config_winavr_inpersian_1.1.5_501.pdf
    406.4 KB · Views: 314
didn't you forget something? :D
 
Status
Not open for further replies.

Similar threads

S
my "precision" current measurement project design review/ check
Replies
5
Views
2K
KeepItSimpleStupid
K
M
12 Hour Digital Clock Project Help
Replies
1
Views
2K
rjenkinsgb
rjenkinsgb
DerStrom8
Calling All FPGA Experts
2
Replies
26
Views
5K
DerStrom8
DerStrom8
HyperText
Change the input voltage of the FPGA
Replies
7
Views
3K
Mikebits
Mikebits
P
SPLD , CPLD and FPGA
Replies
3
Views
4K
ronsimpson
ronsimpson

Latest threads

New Articles From Microcontroller Tips

Back
Top