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Forcing logic gate output

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simon.says

New Member
Hello. I have a question regardind logic gates. Say I have an AND gate. I put low logic level on both inputs, so I expect low level on the output. What happens if I connect high logic level on the output? The IC will be forcing to zero, and I'll be forcing to high.
Similarly, if I have high logic level on the output of a logic gate and connect it to ground, what will happen?
 

AnalogKid

Well-Known Member
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The output stage maximum current rating will be exceeded, the output stage will overheat, and the device will fail. The part might survive a *brief* short circuit on the output, but long-term = death.

ak
 

simon.says

New Member
I see. Thanks for the reply.

What if I put a resistor in series? If the logic output is zero, and I put Vcc on the other end of a series resistor (ouput in series with resistor in series with vcc), would I damage in the same way?
 

MikeMl

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Most Helpful Member
I see. Thanks for the reply.

What if I put a resistor in series? If the logic output is zero, and I put Vcc on the other end of a series resistor (ouput in series with resistor in series with vcc), would I damage in the same way?
Depending on the resistor value, you probably wouldn't damage it, but you likely wont get the result you want, either. Google "logic contention". That is what you are creating.
 

dr pepper

Well-Known Member
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Choose a resistance that would give less current flow than the max of the IC, then things would be OK.
Though care would be needed in design as the o/p wouldnt neccesarily have control.
Also if the and gate is allready loaded up, ie is driving lots of other gates then it may not be possible to do without a driver of some kind.
 

Les Jones

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Hi Simon,
What is the context of your question and what are you trying to achieve ? Some logic families have devices with open collector outputs which may provide a solution to your problem. The outputs of a number of devices with open collector outputs can be connected in parallel. A pull up resistor is required with open collector outputs. The output will only be high is all of the outputs are high. (The output transistors in the non conducting state.) Doing this provides an "AND" function. (It is sometimes called collector oring which would only be true if talking about negative logic.)

Les.
 

AnalogKid

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If the ambient temperature, the max continuous output current, either sinking or sourcing, and the max continuous dedvice power dissipation are less that the values on the datasheet, the part should run fine. Note that for improved long term reliability the current and power should be less than half of the max values. Most logic families can sink (output low) more current than they can source (output high), and have a lower low output voltage at high currents compared to the high output voltage at the same current. This is why it is common for a logic gate to drive an LED by pulling it low rather than high.

ak
 

audioguru

Well-Known Member
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Why don't you say the part number and supply voltage of your logic IC so we can see its maximum allowed output current?
A Cmos CD4081 AND gate with a 3V or 5V supply has very low output current that is much less than its maximum allowed output current.
A TTL 7408 uses only a 5V supply and it will probably smoke and burn if you short its low output to +5V.
 

simon.says

New Member
Thank you all for your answers.
Why don't you say the part number and supply voltage of your logic IC so we can see its maximum allowed output current?
I am not thinking about any particular IC, just wondering what would happen.

Most logic families can sink (output low) more current than they can source (output high)
I think I am missing a basic concept here. Can an input sink and source? Can an output sink and source as well?

Google "logic contention". That is what you are creating.
Thank you. I'll look for it
 

AnalogKid

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Most Helpful Member
For all logic families, a totem pole output can source current when it is pulling a load high, or sink current when it is pulling a load low. An open collector output can sink only; it does not have the upper transistor in the output stage to pull a load high. Some logic devices have tri-state outputs, where both the pull up and pull down transistors are disabled; the output is in a high impedance state and does not sink or source current.

CMOS input stages have such a high input impedance that for all practical purposes they do not source or sink anything. Bipolar logic devices (original TTL, LS, F, etc.) have a common base amplifier for the input stage so whatever is driving them must be able to *sink* current out of the TTL input stage to pull it low. This is why unused input pins of these older logic types float high, whereas unused CMOS inputs float to an unknown state.

ak
 

Tony Stewart

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CMOS output is a complementary Pch/Nch driver each with a certain RdsOn characteristic determined by Vol/Iol and (Vcc-Voh)/Ioh. THis impedance over generations has dropped from 200~300 Ω in CD4xxx series to 50 to 25 Ohms in low voltage types. Thus the power lost in the driver depends on the load impedance and terminal voltage is biased high.

Some designs for high speed data use pull-up-down of equal values to improve over shoot and rise time and thus the terminal voltage is Vcc/2. In another case, ATE can back drive a CMOS output gate to force a state to test the next stage momentarily for automated testing.
 

Pommie

Well-Known Member
Most Helpful Member
If you want to "force an output to one then you add a two input OR gate with one input connected to the output of the AND gate and then the other input can be taken high to make the output high regardless of the output of the AND gate.

Mike.
 
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