Flip flop with set reset input

[Parth86]

Hello
I am confused with this flip flop

When both set and reset inputs is activate, output will be high. because will be same as input on raising edge of clock. When set input activate output will high. When reset input activate output will low. What will the output when both set and reset input is activate?

 

[ronsimpson]

From data sheet of CD4013 or MC14013.
If S and R both = 0 then (clock, D, Q and /Q all work like a DFF should)
If S=1 and R=0 then Q=1, /Q=0
If S=0 and R=1 then Q=0, /Q=1
If S=1 and R=1 then Q=1, /Q=1

 

[alec_t]

What will the output when both set and reset input is activate?

Check the datasheet for your particular flip-flop.

 

[Parth86]

Check the datasheet for your particular flip-flop.

I don't understand case when S=1 and R=1, than Q=1 and /Q=1

 

[alec_t]

If S=1 and R=1 then both outputs will be 1 at the same time.

 

[Dr_Doggy]

S & R dont need the clock to operate they are "asynchronous", thats why there is an x in that column.... cause it doesn't matter , also when setting or resetting it does not matter the value of D either

only J & K need clock , or in this case D. cause they are synchronous they only operate on the clock edges trigger, in this case its a positive edge trigger

 

[Parth86]

Thank very much for helping me

 

[MikeMl]

I don't understand case when S=1 and R=1, than Q=1 and /Q=1

For this type of flip-flop, that is an illegal state (not allowed to happen, never supposed to happen). If you do it anyway, then the disclaimer applies

 

[crutschow]

As Mike stated, having both Set and Reset high at the same time is an illegal state, which is normally avoided..
When the Set and Reset go low, then the output will be determined by the last input to go low.