Good stuff.
Everything has ESR.
e.g. HCxx Logic drivers ( Vol/Iol=ESR) are about 300Ω @5V so with 680 in series it becomes ~1k then five invertors in parallel becomes 200Ω and
10Ω load, R7 becomes 250mVpp out of 5Vpp after harmonics of 5V square wave are low pass filtered. 74ALVxx CMOS logic is around 50 Ω...ALVC2xx logic in ARM chips are around 25Ω.
This R7
10Ω load becomes the source impedance to the Cap being tested in this ESR meter ~10 Ω, which becomes the mid-point of the meter, so no good for comparing low mΩ ESR electrolytic caps or e-caps where ESR is << 100mΩ but faulty standard e-caps might well be >> 1Ω. Each e-cap family usually has a constant ESR*uF product , so larger uF can have lower ESR but better material design can affect ESR greatly. ( e.g. silver content in plates or number of layers in MLM ceramic caps vs monolithic etc.)
Hint ... if you wanted to improve sensitivity of ESR, you might reduce all R values by 10x so you end up with 1Ω load and source impedance with 250mV signal. (1/16W pk) by changing 680's to 68 then changing 10Ω. to 1Ω. with some scope tuning of 1Ω. value, if you wanted more accuracy, (not essential as they use diodes to compress range on meter, instead of step range of source voltage, from which they measure current in the 2nd load R8 , which equals R7.
Inductors have ESR ... often called DCR
Batteries have ESR .. often measured in mΩ for ohmic loss.. as well as chemical saturation drop from float to load voltage.
Crystals have ESR , which affects Q = fc/fBW but cannot be measured in this tester.
Also Caps can have too low ESR for some LDO outputs as it shunts the feedback ripple too much to make it stable and actually introduces a phase shift in the unity gain frequency thus reducing stability or phase margin of some LDO's. They will tell you e-cap ESR range , if this applies.
here is an article on ceramic caps where too low an ESR can raise Q ( amplification of resonance from impulses)
https://media.digikey.com/resources/tdk/tdk-esr-control-multilayer.pdf) which might result in excess ripple.
When using ESR, think of source to load ESR ratio as the important figure to attenuate ripple.
Even LDO's have ESR which is the voltage drop with rise in load current... often observed by senior designers but never specified in design notes.
The series decoupling cap must also be improved if you wanted to reduce range of ESR to 1Ohm by using any plastic cap which have the lowest ESR but also largest size/uF. It's value must be much greater than D.U.T.
OK design but very limited use. I prefer a good LCR meter with 3 1/2 digits accuracy.