Disabling low priority interrupt in high priority ISR

[Urahara]

I have set up a low-pri and a high-pri ISR within a 18F4520 uC using C18.

Once the high-pri ISR is triggered (essentially a 1-minute timer high priority interrupt), I do not want the low-pri ISR to be triggered AFTER the high-pri ISR has completed.

Hence, can I just disable the low-pri interrupt within the high-pri ISR? If not, what is the best way to achieve this?

Thks!

 

[Nigel Goodwin]

It sounds a strange thing to want to do? - are you sure you need to use interrupts at all anyway?.

 

[Urahara]

Hi Nigel

The low-pri interrupt is for data capturing on a pin. Tried the polling method but it seems to be not as fast in capturing data compared to using a interrupt-based mechanism.

Is it a bad idea to do this?

 

[kpatz]

I haven't worked with the PIC18 series but on the PIC16 series the GIE flag is cleared when an interrupt occurs and is set using a RETFIE instruction to return from the ISR. So any interrupt which occurs while in the ISR is blocked until the return from the interrupt.

If the issue is that the low-priority interrupt occurs after returning from the high-priority ISR, just clear the low-priority interrupt's flag before returning from the high-priority ISR.

 

[Nigel Goodwin]

Hi Nigel

The low-pri interrupt is for data capturing on a pin. Tried the polling method but it seems to be not as fast in capturing data compared to using a interrupt-based mechanism.

Is it a bad idea to do this?

It seems a strange way to do it?, surely the data gathering is more important (and MUCH more frequent) than your once a minute clock pulse?.

 

[Urahara]

The data gathering happens much more frequently and rapidly within the 1-minute window. The intent is to collect the data, and once the minute is up, manipulate it and ignore (ie disable) the data gathering low-pri ISR routine. Have actually implemented the codes and seems ok, but not sure if this is the right way to do things.

Hi kpatz, thks for the suggestion. Because the low-pri external event happens rapidly, clearing the interrupt flag within the ISR and hoping to disable the interrupt in the main routine do not always happen. There were cases where, before the main routine has the opportunity to disable the interrupt, the event happens again, and the ISR gets triggered. This may go on for a while. Hence, the idea to turn off the interrupt within the ISR to guarantee it will not be triggered again.

 

[Aussie Susan]

Just to review the way the PIC18F series do their interrupt processing, the fact we are talking about high and low priority interrupts means that you must have the RCON IPEN bit set. This means that the GIEH and GIEL bits of the INTCON register control whether or not the high and low priority interrupts(respectively) are responded to.

When an interrupt occurs, the processor will clear the appropriate bit to prevent nesting of interrupt calls. While I have not tried it myself (basically I would not try to do what you are doing - see below) you should be able to clear the GIEL bit within the high priority ISR to turn off ALL low priority interrupts.

One problem with doing this is that you are not actually addressing the source of the interrupts. When the interrupting peripheral sets if interrupt flag, while it won't trigger an interrupt while the GIEL bit, is clear it will be sitting there and if/when the GIEL bit is set later on, the low priority interrupt will be called straight away.

Rather than playing the the GIEL bit, why not turn off the interrupt enable bit for the peripheral? That way, the peripheral will not try to general any more interrupts but you still let any other (low priority) interrupt process continue if necessary.

Susan

 

[Urahara]

Rather than playing the the GIEL bit, why not turn off the interrupt enable bit for the peripheral? That way, the peripheral will not try to general any more interrupts but you still let any other (low priority) interrupt process continue if necessary.

Susan

This was what I had done, turning off the specific interrupt enable bit within the interrupt service routine. Guess I had been "educated" to enable/disable interrupts from main routines, outside ISRs, and disabling interrupts inside an ISR makes me a little uncomfortable. From your input, seems like I am on the right track?