D flip flop and registers

[Jiyda]

Hello everyone,
I am new to this forum and I have a question regarding the hardware of a computer.
I am reading this book : **broken link removed**
It's composed of projects that show you how to build a modern computer using Nands.
Now, I'm in the chapter about sequential chips particularly flip flops and registers;
Here is a section of the book :
"In this book we use a variant
called a data flip-flop, or DFF, whose interface consists of a single-bit data input
and a single-bit data output. In addition, the DFF has a clock input that continuously changes according to the master clock’s signal. Taken together, the data
and the clock inputs enable the DFF to implement the time-based behavior out(t) = in(t-1), where in and out are the gate’s input and output values and t is the current
clock cycle. In other words, the DFF simply outputs the input value from the previous time unit"
I didn't really understand what the inputs and the outputs of this chip are: is t the current time or the current cycle? what about the data input how is it used?
And for the register the book states:
"A register is a storage device that can ‘‘store,’’ or ‘‘remember,’’ a value
over time, implementing the classical storage behavior out(t) = out(t -1)"

When would it stop, to me it look like an infinite loop, the output is the previous output, but the previous output is the previous previous output?

Thanks and hope to hear from you soon!

 

[Gary B]

I am not too happy with the definition of the D flip lop. The D is supposed to stand for delay. What is at the input at clock time 1 is at the output at clock time 2. Most D-Flip Flops are built with complimentary outputs (Q and not Q). If you connect the not Q to the input, you get what you described. However, what you failed to notice is that the Q output is mimicking the clock at ½ the frequency so you have built a divide by 2 device.

 

[BrownOut]

I didn't really understand what the inputs and the outputs of this chip are: is t the current time or the current cycle? what about the data input how is it used?

"t" is the time of the current cycle. The output of the flip flop remains at the value of the input when the input was sampled by the clock edge. So, although the input may change, the output remains at the sampled value. Hence, the flip flow is a one digit memory cell.

 

[MikeMl]

Read **broken link removed**

It says: The logic state at the DATA input is transferred to the output on the rising edge of the CLOCK signal.

Look at the attached. Note what the Output does as a function of the state of the Data line when the Clock line goes from low to high (rising edge)

 

[BrownOut]

Your post made me re-read mine, and I realized I wrote "input" where "output" belongs, and visa-versa. I have corrected my post.