Current Draw of PIC18F2450

[wuchy143]

Hi All,

I"m trying to verify my experimental current draw of the PIC18F2450 which i measure to be ~12mA. Looking at the datasheet I can't find anything remotely close to what I"m measuring using a 4MHz crystal. What am I missing?

https://media.digikey.com/pdf/Data%20Sheets/Cypress%20PDFs/CY7C63001A_63101A.pdf?cshift_ck=null&client_id=5042

 

[Nigel Goodwin]

What else do you have in the circuit?.

 

[wuchy143]

What else do you have in the circuit?.

I'm measuring the current in the chip two different ways. First way is I lift the power pin on the PIC and just put my meter in series from USB+5V to the lifted power pin on the PIC.(yields 12mA) The second way I measure the current of the PIC is I measure the overall current for the USB keyboard which has an 8052...100 or so LED's(draw 2-3mA each), 74HC74, FET for LED's, PWM PIC....and that's about it(only a USB keyboard). Then I take out the USB PIC(it's socketed) and measure the current. Then I take the difference. Both ways I get the same current so I"m confident my experimental current draw is in the ballpark. Just wish I could verify it with the datasheet to make sure we're not doing something bad in HW or FW. Thanks for the reply!!

-mike

 

[Nigel Goodwin]

You haven't explained what's connected to the PIC, it could easily be feeding the current out of it's I/O - 10mA out to an LED, means 10mA extra current to the PIC.

 

[wuchy143]

The pic is only used as a USB controller. So it directly plugs from the PIC to a USB port on a computer. Though, it's connected to the 8052(89S52) tx and rx pins mainly on my board. Anything else is required by the datasheet to strap it correctly. Pictures are easier sometimes

 

[Nigel Goodwin]

What are W23/24/25?

Also, where are your supply decoupling capacitors?

 

[Exo]

Did you set those unconnected pins high or low in software ? You should not leave them floating (as inputs), that also causes increase in current consumption.

 

[wuchy143]

W23, W24, and W25 are not used in this design. They are all set low as I recall.

Decoupling caps are there just not in the area shown. I have them all in the bottom right of my schematic to try and keep things neat. When I go into layout I make sure they are all placed near their appropriate chips/pins.

The drift I'm getting from you guys is that I'm indeed drawing too much current on this chip?? Let me talk to the F.W guy and see what he thinks. I can do some code but I mainly do the hardware for our products and he would better understand what could be going on.

 

[Nigel Goodwin]

Did you set those unconnected pins high or low in software ? You should not leave them floating (as inputs), that also causes increase in current consumption.

As far as I'm aware that doesn't apply to PIC's, only to CMOS logic gates - there was a LOT of discussion years ago (MANY years ago) on the PICList. As I recall it makes next to no difference if you set them as inputs or outputs, or high or low.

 

[wuchy143]

As far as I'm aware that doesn't apply to PIC's, only to CMOS logic gates - there was a LOT of discussion years ago (MANY years ago) on the PICList. As I recall it makes next to no difference if you set them as inputs or outputs, or high or low.

Hmmm.. didn't knwo that. So are you saying if you have logic gates which you don't use on a chip you need to strap them high or low(pullup or pulldown) or you will draw more current than needed when they are floating?

 

[Nigel Goodwin]

Hmmm.. didn't knwo that. So are you saying if you have logic gates which you don't use on a chip you need to strap them high or low(pullup or pulldown) or you will draw more current than needed when they are floating?

On CMOS gates (4011 etc.) if you leave inputs flaoting they can drift into an analogue region, where the chip will take many times it's usual current - but this doesn't apply to PIC's.

 

[spuffock]

I'll get shouted at for this- just wait and see.
While monitoring the current, rub a plastic comb on your sleeve and approach the pic with it. If the current varies according to the distance of the comb, then you've got a floating input problem. Then you can set about finding out which one it is, a megohm resistor connected to ground is useful for this. then assign it a pullup resistor, or make it an output.
Don't get too close with the comb, if youget a current change youre near enough.

 

[RCinFLA]

A CMOS stacked Pch - Nch totum pole will have shoot through current due to partial turn on of both top and bottom devices when input is floated between the supply.

You need a high value pull resistor if any of the external connected devices tri-states (floats) its output. For example, I2C serial interface allows multiple I2C interface devices on the same pins so each device tri-states when inactive. There has to be pull up resistors on these pins.

Any pins designated as inputs must be pulled to supply or ground, either direct connect or through a pull resistor. I am not sure about the PIC but some processors have configurable input pull up/dwn resistors incorporated in I.C.

General I/O's on processors are a standard circuit that can be configured as input or output. If configured as output it should be programmed high or low and not allowed to tri-state unless there is a pull resistor.

 

[Nigel Goodwin]

Back last century this was debated for a LONG time on the PICList, the outcome was that it made no difference whatsoever on a PIC, either setting pins as outputs (high or low), or setting them as inputs, with or without pullup/down resistors.

 

[RCinFLA]

Back when 1 to 3 micron CMOS process was being used the issue was not as noticable.

As geometry shrinks, the ratio of gate threshold to Vdd becomes less and less and the transition of drain current to Vgs is softer.

For latest submicron CMOS process (<65 nm) it has become a big issue. Even with gate pulled to source there can be significant leakage. For portable devices this has become a major problem and techniques are being employed that disconnects Vdd from functional sub-blocks when they are not in active use to reduce chip leakage current.

Most sub-micron processes employ two or three different gate threshold device options. This requires extra I.C. processing steps. Low threshold devices are selected for speed (with side effect of poor leakage performance). High threshold devices are selected for lower leakage (with side effect of reduced speed performance).

I am pretty sure PIC's are not made with deep sub-micron process but they are probably in 150 to 300 nm range. I don't believe there are any 3 micron fabs still in existance and maybe just a couple of old 1 micron fabs still running in the whole world.