So I've always thought there was only one current flowing through a MOSFET in Linear mode and Saturation -- I_d, but why is there an I_s here in this diagram?
Rs is part of the bias stabilization. It is usually bypassed with a capacitor if you want max voltage gain in the stage. Otherwise, the voltage gain is Rd/Rs.
Id and Is are very close, but not equal. Part of Id goes out to the load and not through the source. Also, while the gate current is very low, it does exist, and becomes part of Is that is not coming through the drain.
In the circuit in post #1, the gate current has an AC component.
In a power MOSFET the gate capacitance can exceed 1 nF.
At a frequency of 10 kHz this is an impedance of only 16 kohm.