Counter using d flip flops

[Tony Stewart]

For clarity remember that requires 2 previous stage clocks for a rising edge on the next stage. Thus initial Qbar is correct for clocking the next stage which initially is high then low then rises to count the next binary(2) event.

Take a look at the CD4040 and 4060 ripple counters.

 

[spec]

For clarity remember that requires 2 previous stage clocks for a rising edge on the next stage. Thus initial Qbar is correct for clocking the next stage which initially is high then low then rises to count the next binary(2) event.

Take a look at the CD4040 and 4060 ripple counters.

All of the D type flipflops in a ripple counter feed their /Q out put to the clock input of the following flipflop.

spec

 

[ericgibbs]

Hello ericgibbs
Thank you for your response. I am asking for circuit that I have posted in my first post. some day ago I asked for ripple counter in another forum

My understanding is the OP is not asking for a conventional binary ripple counter, but a 'counter' as drawn in his earlier posts.
ie: the 2nd F/F clock is derived from the 1st F/F Q0 output.

I have posted a sim of this version and explanatory text.

E
Added text.

 

[Tony Stewart]

All of the D type flipflops in a ripple counter feed their /Q out put to the clock input of the following flipflop.

spec

correct, that's what I said ..

If you cascade from Q to D, the output toggles from initial Q=0 on the 1st transition , not 2nd but after this still becomes /4 if this is the only output.

 

[spec]

correct, that's what I said ..

If you cascade from Q to D, the output toggles from initial Q=0 on the 1st transition , not 2nd but after this still becomes /4 if this is the only output.

This does not make sense. You make no mention of the CLK so in fact the configuration you describe will do nothing. But in any case, if you connect the Q output from one flipflop to the D input of the next flip flop you get a shift register not a counter, assuming all the D type flip flops are clocked at the same time that is.

Let me emphasize that in a binary ripple counter (a divider is not being discussed here) you connect the /Q (Q inverted) of a flip flop to the CLK input of the following flip flop and that is all there is to it.

With a synchronous binary counter all the flip flop clocks are connected together so that all flip flops are clocked at the same time. You then need extra logic to implement a binary count.

spec

 

[Parth86]

2 bit Ripple counter

4 bit serial in serial out shift register

 

[ericgibbs]

hi vead,
Are you asking a question about those counter images.?
E

 

[Parth86]

hi vead,
Are you asking a question about those counter images.?
E

Yes. I have questions but I will ask later. First I have questions for below images

When clock low, output does not change
When clock raise, output will same as input
When clock high, output does not change
When clock falling, output does not change

This is logic to understand D flip flop. D input is connected to inverted output. So we don't know the input data weather it is 0 or 1. If data is 1 than output will 1 means high on raising edge. And if data is low than output will low means 0 on raising edge. So how can we say that the output is high or low on the raising edge When we don't know what is input data? .
Please clear the doubt

 

[ericgibbs]

When clock low, output does not change
When clock raise, output will same as input
When clock high, output does not change
When clock falling, output does not change

This is logic to understand D flip flop. D input is connected to inverted output. So we don't know the input data weather it is 0 or 1. If data is 1 than output will 1 means high on raising edge. And if data is low than output will low means 0 on raising edge. So how can we say that the output is high or low on the raising edge When we don't know what is input data? .
Please clear the doubt

hi,
The Clock changes the state of the F/F ONLY on the High rising edges.
The small triangle on the clock shown on the symbol of the F/F means its a High Going Clock F/F.

When the Clock is a steady High or Low the F/F is not switched.

The Clock will Set the 'Q' output to the same state as the 'D' input.
So when the /Q is connected to the 'D' input , on every clock pulse rising edge the F/F will switch over.

The 'D' input must always be connected.

For example if you connected the 'D' input only to +V , a logic high, after the 1st clock pulse the 'Q' will always be High and never change for further clock pulses.

For example if you connected the 'D' input only to 0v , a logic low, after the 1st clock pulse the 'Q' will always be Low and never change for further clock pulses.

E

 

[Tony Stewart]

sorry for missing by huge brainfant error and assumptions of referring to cascaded N stage ripple counter . When cascaded traditionally it must also use the Qbar cascade outputs to the next stage to generate a binary up counter like the CD4020 series.

I meant Q to next stage CLK sorry.
When I said "If you cascade from Q to D, the output toggles from initial Q=0 on the 1st transition , not 2nd but after this still becomes /4 if this is the only output."

I was implying the parallel outputs of N ripple count stages (Qbar to D) stages with Q output to next D stage would no longer be a binary sequence, but still a /2N counter.

Since the initial dwg. did this but not your subsequent correct one.

BUT if you only used the final or intermediate stage as /2 stages, each one is a square wave of 1/2N input frequency, regardless if cascading the Q or Qbar to next stage Clk.

i.e. Qn+1 toggles on the 1st transition of Qn not the 2nd, so it is essentially phase shifted but does not affect each stages /2 function. Thus as was done in this thread the schematic was changed in this thread from using Q to drive the next stage to the proper output Qbar, Although each stage still uses Qbar to D for feedback.

better now? sorry I mentioned it...
"

This does not make sense.

spec

 

[Parth86]

hi,
The Clock changes the state of the F/F ONLY on the High rising edges.
The small triangle on the clock shown on the symbol of the F/F means its a High Going Clock F/F.

When the Clock is a steady High or Low the F/F is not switched.

The Clock will Set the 'Q' output to the same state as the 'D' input.
So when the /Q is connected to the 'D' input , on every clock pulse rising edge the F/F will switch over.

The 'D' input must always be connected.

For example if you connected the 'D' input only to +V , a logic high, after the 1st clock pulse the 'Q' will always be High and never change for further clock pulses.

For example if you connected the 'D' input only to 0v , a logic low, after the 1st clock pulse the 'Q' will always be Low and never change for further clock pulses.

E

Hello
I am sorry for taking so much time to understand . Now I have only one doubt. Still I don't understand how second flip flop work. I know the output of first flip will be input for second flip flop. If we apply logic 0 to clock, than second flip doesn't change output . Also we apply logic 1 to clock of second flip, output does not change because d flip flops only work on raising edge not low and high state of clock

 

[MikeMl]

vead,

Assume that when a flip flop is first powered up is that it comes up in either of two states; Q=0 or Q=1. (Forget about metastability for now).

All you can say about what happens on a rising edge of the clock is that if the flip flop wired with Q~ to D, it goes to the opposite (Boolean not) of its present state. This is called a "Toggle".

If you are worried about building a counter where the actual initial state matters (after power-up), then use a flip flop that has asynchronous SET and CLEAR inputs, like a '4013, and then explicitly preset the counter flip-flops to a known state before applying the first clock edge.

If you are using a ripple counter as a frequency divider, then the initial state of the counter may not matter.

 

[spec]

Yes. I have questions but I will ask later. First I have questions for below images
View attachment 100907

When clock low, output does not change
When clock raise, output will same as input
When clock high, output does not change
When clock falling, output does not change

This is logic to understand D flip flop. D input is connected to inverted output. So we don't know the input data weather it is 0 or 1. If data is 1 than output will 1 means high on raising edge. And if data is low than output will low means 0 on raising edge. So how can we say that the output is high or low on the raising edge When we don't know what is input data? .
Please clear the doubt

vead, you will get nowhere if you do not listen to what we say. Your first diagram is not a ripple counter. In a ripple counter, made with positive edge triggered flip flops, the /Q output of each flip flop goes to the clock input of the following flip flop. If you will not or cannot accept this fundamental concept, I will leave you in confusion. This thread has already wasted a lot of time arguing to and fro about a simple and fundamental couple of concepts that even the most basic book on logic design describes.

spec

 

[Les Jones]

Hi vead,
Eric has given a very clear description with his diagram of how YOUR circuit works in post #6 and I have described it in test in post #9 We have both pointed out that YOUR circuit is not a normal ripple counter as you have the clock input of the second flipflop connected to Q output when it should be connected to the NOT Q output for it to be a normal ripple counter. In your post #31 you say "the output of first flip will be input for second flip flop" The input (D input) of both flipflops is connected to their own NOT Q outputs. The Q output of your first flipflop is connected to the clock of the second flipflop. As a result the second flipflop will change state when it's clock goes from LOW to HIGH. I think yoau may be missing the point that the change occures on the LOW TO HIGH TRANSITION of the clock. It does not change state if the clock is at a steady low or steady high. It also does not change state on a HIGH to LOW transition of the clock.

Les.

 

[MikeMl]

...Your first diagram is not a ripple counter. ...

Yes it is a ripple counter. It just happens to be Down Counter instead of an Up Counter. Look at this for an explanation:



The "Dec" column in the state tables is just the "decimal encoded" value of the two flops, with X as the lsb and Y as the msb... Obviously, X1 behaves identically to X2. Note that I didn't make any attempt to initialize the two flops to any particular state. These are the "default" initial states that LTSpice comes up with...

Both counters divide the input clock by four, so it doesn't matter which connection is used if this is the goal... It only matters if you need to implement a specific counting sequequence.

Questions for vead:
How many different divide-by-4 counting sequences can you make using only two flipflops?
Can you draw all of them?

 

[Les Jones]

Good point Mike. I han't spotted it was counting down. I stand corrected.

Les

 

[Parth86]

Yes it is a ripple counter. It just happens to be

Questions for :
How many different divide-by-4 counting sequences can you make using only two flipflops?
Can you draw all of them?

Your questions was different before editing. I think you are asking how many types of counter can we make using two flip flops. Suppose there is two d flip flops, it means we are counting 00 to 99 digits, we can count 00 to 99 up counter and another example 99 to 00 down counter. Also we can make different counting sequences,

 

[Les Jones]

Two flipflops can only count from 0 to 3. To count up to 99 you would need 7 flipflops which would count from 0 to 127 decimal (0 to 1111111 binary) 0 to 177 octal ) (0 to 3F hexidecimal)

Les.

 

[Parth86]

Two flipflops can only count from 0 to 3. To count up to 99 you would need 7 flipflops which would count from 0 to 127 decimal (0 to 1111111 binary) 0 to 177 octal ) (0 to 3F hexidecimal)

Les.

Yes you are correct. 00 to 11up counter and 11 to 00 down counter

 

[MikeMl]

... 00 to 11up counter and 11 to 00 down counter

So how about these two? Note that they are topologically identical; the only difference is how I labeled X and Y...



2 flops can have at most 2^2=4 total states. How many can 5 have? Asking about states here, not sequences...