# Counter using d flip flops

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#### Parth86

##### Member
Hello
I just want to know how does counter make using flip flop. I understand D flip flop work raising edge or falling edge of clock

Here I understand the logic of D flip flops

I am having difficulty to understand operation of d flip flops in counter. I don't understand why the data input connect to inverted output also I don't understand operation of second flip flop. Please someone help me

#### ericgibbs

##### Well-Known Member
The D [ data] input has to be at the Inverse level state in order for the bistable to change state on the next rising edge of the clock pulse.
On Reset, the /Q is at logical '1' so the the next clock edge will toggle Q and /Q,
E

EDIT:
Look at this image of the internals of a 4013 F/F

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#### Tony Stewart

##### Well-Known Member
This is a classic divide /2 cascaded twice.

When inverted output is delayed on each clock rising edge, the input "toggles" or alternates polarity. thus for each clock 010101 each Q output becomes half the frequency.

#### ericgibbs

##### Well-Known Member
hi again,
The clock to the second F/F is incorrect for a simple binary counter.
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#### Tony Stewart

##### Well-Known Member
the 2nd FF is correct for an asynchronous cascaded ripple counter.
i.e. a simple divide by 4 clock out.

#### ericgibbs

##### Well-Known Member
This is the sequence he will get using those connections..
The Op has also been asking about a 'binary' counters on another Forum.

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#### Parth86

##### Member
Thank you for helping me. I understand that first flip flop change state at raising edge of each clock pulse. Still I am confused how the second flip flop work. When it change state and when it doesn't change state. If possible can someone explain with logic?

#### ericgibbs

##### Well-Known Member
Thank you for helping me. I understand that first flip flop change state at raising edge of each clock pulse. Still I am confused how the second flip flop work. When it change state and when it doesn't change state. If possible can someone explain with logic?
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#### Les Jones

##### Well-Known Member
In your diagram with 2 flip flops we will start with both flip flops in the reset state. (Both Q outputs low.) (Normally the second flip flop clock would be connected to the NOT Q output of the first but I will show what happens with the way you have it connected.

Initial state 0,0
First rising edge of input clock. f1 Q output goes high. This causes f2 also to go high as it sees a rising edge on it's clock input. (State after clock pulse 1,1)
Second rising edge of input clock f1 Q output goes low. f2 does not change as it sees a negative edge on it's clock input. (State after clock pulse 0,1)
Third rising edge of input clock. f1 Q output goes high. This caused f2 to go low as it sees a rising edge on it's clock input. (State after clock pulse 1,0)
Fourth rising edge of input clock. f1 Q output goes low. f2 does not change as it sees a negative edge on it's clock input. (State after clock pulse 0,0) (This is the same as the starting state.)

So you see that 4 clock pulses into f1 are required for the 2 flip flops to return to their original state. If you had connected the clock input of f2 to the NOT Q output of f1 then the sequence would be a normal binary count.

Les.

#### ericgibbs

##### Well-Known Member
Look over this image.
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#### MrAl

##### Well-Known Member
Hi,

I might be able to help a little here.

First the operation of a single D flip flop should be completely understood. Then, to understand how two work in tandem you only need to look at the two outputs at the same time to see what they are doing with each input clock pulse.

Starting with a single D-FF, when the D is high the Q clocks to a high and the Q' clocks to a low (Q'=notQ or Qnot).
Nothing else happens yet, just that, except of course that the D changes from a high to a low because the Q' went low now.
So look at it again and see that now the D is low.

The next clock (rising clock edge) makes the FF clock the Q into a low now because the D input is low. That also manes teh Q' high again, which makes the D input high again.

So see now we are right back where we started, with the D high and the Q low and the Q' high.

What could possibly happen next? Same thing. The process repeats, so with every clock edge the Q output changes state and so does the Q'. If you look at the frequency the Q output goes high with one clock and low with the next clock, so therefore it takes 2 clocks to get one cycle out of the Q, which means the Q frequency is 1/2 of the clock frequency.

Now we come to the second stage.
The second stage FF works exactly like the first, except it gets it's clock from the Q of the preceeding stage. That means it's output Q will only change once per output of the first FF, which means the frequency of that Q will be 1/2 of the first FF or 1/4 of the original input clock frequency.

If we look at the stages of each Q while this is happening, we'll see:
00
01
10
11

in binary on the two Q outputs. Thus we have a 2 bit counter.
The type of counter in this case is a binary ripple counter.

#### Parth86

##### Member
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Hello ericgibbs
Thank you for your response. I am asking for circuit that I have posted in my first post. some day ago I asked for ripple counter in another forum

#### ericgibbs

##### Well-Known Member
OK, so look at post #10 image, if have a question please refer to the diagram, so that we can follow.
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#### Parth86

##### Member
OK, so look at post #10 image, if have a question please refer to the diagram, so that we can follow.
E
OK, At second raising edge of clock pulse why the second flip flop is high and at third raising edge of clock pulse why it become low ( I am asking about logic, not frequency)

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#### Parth86

##### Member
Oh my big mistake that is incorrect diagram, I am really sorry. output q is connected to input of next flip flop. Eric posted correct diagram in his post.

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#### spec

##### Well-Known Member
Oh my big mistake that is incorrect diagram, I am really sorry. output q is connected to input of next flip flop. Eric posted correct diagram in his post.
The diagram I posted is a ripple counter made from D type flip flops. /Q is connected to the clock input of the next D type flip flop, not Q. The diagram shows a classic arrangement for a ripple counter and is correct.

spec

#### Parth86

##### Member
The diagram I posted is a ripple counter made from D type flip flops. /Q is connected to the clock input of the next D type flip flop, not Q. The diagram shows a classic arrangement for a ripple counter and is correct.

spec
As per my knowledge, that is not correct diagram for ripple counter. In ripple counter, only first flip flop is connected by external clock, all subsequent flip flops are clocked by output of preceding flip flops

#### ericgibbs

##### Well-Known Member
OK, At second raising edge of clock pulse why the second flip flop is high and at third raising edge of clock pulse why it become low ( I am asking about logic, not frequency)
On both F/Fs the /Q is connected to the 'D' input, so every rising edge clock input will toggle the outputs of the F/F

The first F/F is clocked from the Clock pulse input.
If /Q0 then 'D' is High the next clock pulse will change the /Q to a Low, so 'D' will also be Low.

The second F/F works in the same way , but the FF2 clock input is from Q0 output.

E

As per my knowledge, that is not correct diagram for ripple counter. In ripple counter, only first flip flop is connected by external clock, all subsequent flip flops are clocked by output of preceding flip flops
You are correct for a standard binary ripple counter, but your counter is not connected the same way.

#### spec

##### Well-Known Member
As per my knowledge, that is not correct diagram for ripple counter. In ripple counter, only first flip flop is connected by external clock, all subsequent flip flops are clocked by output of preceding flip flops
That is exactly what the diagram in post #15 does. It is the classic schematic for a ripple counter and it is called a ripple counter because all the clocks ripple along the counter and the delay from the input clock to the Q output transition of the last flip flop is equal to tCK/Q * N, where, tCK/Q = the propagation delay from the rising edge of the clock to a change in the Q output of each D type flip flop, and N is the number of stages in the ripple counter.

On the other hand, in a synchronous counter, the input clock goes to each flipflop, and all flipflops are clocked at the same time. Thus the propagation delay does not accumulate and the delay from clock to any Q is always tCK/Q.

In high speed complex designs synchronous circuits, mainly counters and shift registers, are always synchronous. All microcontrollers/microprocessors are essentially synchronous.

Just imagine if the program counter in a microprocessor were a 64 bit ripple counter: the Arithmetic Logic Unit (ALU) would execute an instruction in say 10ns and, if each D type flip flop in the program counter had a propagation delay of say 10ns, that would mean that the ALU would have to wait 64 * 10ns = 640ns, before the next instruction could be available for execution. So, instead of a microprocessor capable of 100 Megga operations per second, the microprocessor would only be capable of 1.6 Kilo operations per second.

spec

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