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JK FLIP FLOPS

sxy

Member
HI

Figure A of Question 6 shows a diagram of a circuit made up of JK FLIP FLOPS components, which respond to the
.decrease of each CLOCK

For the SI input, the DATA information signal, shown in Figure B, is provided .
Assume that at time T = 0
Q1 = Q2 = Q3=0.
A. Indicate the purpose of the circuit shown in Figure A.(In the file attached).
B. Indicate a possible use of the circuit shown in Figure A.
Thanks a lot
 

Attachments

  • JK FLIP FLOPS.pdf
    274.2 KB · Views: 60
Last edited:

sxy

Member
So can you drew the right waveforms of Q1;Q2; and Q3?
In all cases j1=j2=j3=1
and k1=k2=k3=0
so q should be high.
Why am I wrong?
j=1 and k=0 is reset and not setup up as you said.
thanks a lot
 
Last edited:

rjenkinsgb

Well-Known Member
Most Helpful Member
There is no point someone drawing it if you do not understand why they work as they do.

The clock edge is an instantaneous event.

At that instant, J is high (and K low) for the first stage only.

It's Q [Q1] changes after the clock edge; it is cause-and-effect; the effect cannot take place until after the cause has.
 

rjenkinsgb

Well-Known Member
Most Helpful Member
You were correct with the modified sketch.

Q (and /Q) change immediately after the clock edge; typically a few nanosecond in real devices.
The J & K (or D for D type) inputs need to be valid for typically a few nanoseconds before the clock edge, to be accepted.

So, the input data is shifted through one stage per clock pulse; that's what a "shift register" does:

3-s2.0-B9780750645829500081-f07-23-9780750645829.gif
 

sagor1

Active Member
You changed the DATA something that is is not allowed to do.
I drew only q1 q2 and q3.
Your own PDF (second one) is showing the same effect, the input data is being shifted by each stage as it is clocked. Just happens you have 3 stages instead of 4 as shown by RJen. Number of stages is irrelevant, it is the concept of shifting that is being shown.
 

rjenkinsgb

Well-Known Member
Most Helpful Member
You changed the DATA something that is is not allowed to do.
That is a diagram showing how a shift register works, using JK type flip flops.

It's not an answer to your homework, it's education; the data at the input (whatever it is) will move one stage along with each clock cycle.

More examples:
shift_reg_2.png


shift-register-timing-diagram-54164.png
 
Last edited:

Papabravo

Well-Known Member
You changed the DATA something that is is not allowed to do.
I drew only q1 q2 and q3.
Why not? Is that a realistic occurrence in a real system? What would be the point in filling up a register with either 1's or 0's and not letting the input change. Where did you acquire such a quaint notion?
 

sxy

Member
Hi
A. What is the purpose of this system?(In the attached file).

B. The table below shows the initial state of the input IN and of the outputs Q0, Q1 and Q2.
Copy to your notebook the table and complete in it the condition of each of the finds for
Knocks 1-5.

C. Copy to your notebook the clock pulses in Figure B and draw, one below the other, the shape
Wave at each of the outputs Q0, Q1, Q2, for pulses 1–5.
 

Attachments

  • Image_0008920220716213136.pdf
    474.2 KB · Views: 15

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