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Conundrum trying to reset cascaded counters!

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PConst167

Member
Hi friends,

I have two 12-bit ripple counters cascaded together (74HC4040), and when they reach a certain 18bit value, I reset them by first setting a flip flop, and then at the next clock edge resetting the counter. This has worked for me before, but now it just isn't working! I have no idea why this could be.

The reset signal is 100ns, which is much more than the 45ns required.

Does anyone have any ideas or have gone through similar situations ?
 

ChrisP58

Well-Known Member
Hard to say without seeing the schematic, but my first guess is that you may have a race condition where the flip-flop inputs needed to produce the reset pulse are changing at the last nanosecond.

What is your test setup? Simulator or protoboard?
 

PConst167

Member
Hard to say without seeing the schematic, but my first guess is that you may have a race condition where the flip-flop inputs needed to produce the reset pulse are changing at the last nanosecond.

What is your test setup? Simulator or protoboard?

The flop is not in a race condition... there is enough time for things to settle. I have seen a design where a guy attached a capacitor in parallel and a resistor in series with the reset signal going to the counters.

Look at this image below. Thats how he's resetting the cascaded counters... Why ? And what should be the value of the resistor please anyone ?

 
Last edited:

crutschow

Well-Known Member
Most Helpful Member

PConst167

Member
Show the circuit for that.
I don't have schematics. I'm looking for general advice on resetting cascaded counters which is a common thing that is done in digital circuits. You can see the circuit above where someone uses a capacitor in order to do it and I dont understand exactly why except to stabilize the reset signal and hold it up for a while
 

ChrisP58

Well-Known Member
A capacitor can provide a delay, with time being T = R x C. But the resistance is that of the source. In this case, wherever the RESET signal is coming from. And that is not shown. If RESET is coming straight from the output of another logic device, then the effective source resistance will be only a few ohms.

The resistance in the circuit fragment that you posted is on the load side of the capacitor, and will have virtually no effect on the delay, as it is on the wrong side of the capacitor to be part of the equation.

If the variable resistance of R6 had an effect on the function of the circuit authors reset behavior, then it was creating an RC delay with the stray and parasitic capacitance of his PCB, wiring, and pin capacitance.
 

spec

Well-Known Member
Most Helpful Member
That reset circuit is nonsense and may be a poor attempt to eliminate switch bounce if a manual reset is used.

Although the clock input of the CD4040 has an unlimited rise and fall time, because the clock input is probably a Schmidt trigger, strangely, the reset does not allow slow rise and fall times.

The consequences of a slow rise and fall time on the reset input are that the input gate may be in the linear region long enough to oscillate, which can put the CD4040 into an undefined state.

The CD4040 is not a particularly fast divider, especially with 5V supply lines- you do not say what supply lines are being used. The CD4040 is probably optimum at 10V supply lines, but the gate linear region would then be much wider and the problem with slow rising and falling edges on reset would be exacerbated.

Also, without good grounding, decoupling, and a generally compact layout, all kinds of problems may arise, and remember that the figures you see on the data sheet are under optimum conditions.

Just one word about circuits you see in books, magazines and on the net. Don't think that just because a circuit is published it is correct- the opposite is often the case.:eek:

spec

DATASHEET
(1) http://www.ti.com/lit/ds/symlink/cd4040b.pdf
 

PConst167

Member
That reset circuit is nonsense and may be a poor attempt to eliminate switch bounce if a manual reset is used.

Although the clock input of the CD4040 has an unlimited rise and fall time, because the clock input is probably a Schmidt trigger, strangely, the reset does not allow slow rise and fall times.

The consequences of a slow rise and fall time on the reset input are that the input gate may be in the linear region long enough to oscillate, which can put the CD4040 into an undefined state.

The CD4040 is not a particularly fast divider, especially with 5V supply lines- you do not say what supply lines are being used. The CD4040 is probably optimum at 10V supply lines, but the gate linear region would then be much wider and the problem with slow rising and falling edges on reset would be exacerbated.

Also, without good grounding, decoupling, and a generally compact layout, all kinds of problems may arise, and remember that the figures you see on the data sheet are under optimum conditions.

Just one word about circuits you see in books, magazines and on the net. Don't think that just because a circuit is published it is correct- the opposite is often the case.:eek:

spec

DATASHEET
(1) http://www.ti.com/lit/ds/symlink/cd4040b.pdf

Spec, the IC is actually the 74HC4040, he just didn't write it there. The reset comes from another 74HC logic gate, a XOR gate to be precise.
 

PConst167

Member
A capacitor can provide a delay, with time being T = R x C. But the resistance is that of the source. In this case, wherever the RESET signal is coming from. And that is not shown. If RESET is coming straight from the output of another logic device, then the effective source resistance will be only a few ohms.

The resistance in the circuit fragment that you posted is on the load side of the capacitor, and will have virtually no effect on the delay, as it is on the wrong side of the capacitor to be part of the equation.

If the variable resistance of R6 had an effect on the function of the circuit authors reset behavior, then it was creating an RC delay with the stray and parasitic capacitance of his PCB, wiring, and pin capacitance.
It is coming from a 74HC XOR gate. I removed it because it was connected to the reset logic. Why is it the resistance of the source if there is a variable resistor there as well ? I don't understand the circuit very well. Suppose reset goes high, then the capacitor is charged up. Then when reset goes low, the output impedance of the logic gate connected to the reset signal will probably be lower than the variable resistor so little current will flow through the resistor... right ?
 

spec

Well-Known Member
Most Helpful Member
Spec, the IC is actually the 74HC4040, he just didn't write it there. The reset comes from another 74HC logic gate, a XOR gate to be precise.
Ah yes, 74HC4040, like you said in the opening post.

All the same, the reset circuit is not correct.

In general, it is not acceptable/good practice to put capacitance across a logic line or to put resistance in series with a logic line, as both corrupt the logic signal. 74HC logic chips have a very high input independence at DC but the input impedance drops with frequency.

Also, reset circuits are simple to design and implement, so why not do the reset professionally.:)

spec
 
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PConst167

Member
Ah yes, 74HC4040, like you said in the opening post.

All the same, the reset circuit is not correct.

In general, it is not acceptable/good practice to put capacitance across a logic line or to put resistance in series with a logic line, as both corrupt the logic signal. 74HC logic chips have a very high input independence at DC but the input impedance drops with frequency.

Also, reset circuits are simple to design and implement, so why not do the reset professionally.:)

spec

Spec, can you please help me to design a reset logic? It's just for 2 cascaded 12bit ripple counters. They need to reset at the same time. I have been working for almost a month now on a composite video generator and it's almost working. It's even sending bits to the TV via a shift register. But when I thought it would finally work, my reset didn't work and my frame frequency went to 30Hz rather than 50Hz and I get a nasty black strip rolling across the screen :D

The problem is that I don't have schematics. I made it straight on the breadboard from my head as I went. It's basically 2 counters that count pixels. 512 pixels * 312 lines. The vertical sync is output at the first 4 lines and so on.

I think the problem is really the fact that when I send the reset signal to my 2 cascaded counters, they are not resetting at the same time.

How do I make them reset at the same time ?? :(
 

spec

Well-Known Member
Most Helpful Member
Spec, can you please help me to design a reset logic? It's just for 2 cascaded 12bit ripple counters. They need to reset at the same time. I have been working for almost a month now on a composite video generator and it's almost working. It's even sending bits to the TV via a shift register. But when I thought it would finally work, my reset didn't work and my frame frequency went to 30Hz rather than 50Hz and I get a nasty black strip rolling across the screen :D

The problem is that I don't have schematics. I made it straight on the breadboard from my head as I went. It's basically 2 counters that count pixels. 512 pixels * 312 lines. The vertical sync is output at the first 4 lines and so on.

I think the problem is really the fact that when I send the reset signal to my 2 cascaded counters, they are not resetting at the same time.

How do I make them reset at the same time ?? :(
I will have a look at a reset method PC.:)

Am I correct in saying that the ripple counters are being clocked from a 5MHz clock?

What is the source of the reset signal?

spec
 

PConst167

Member
I will have a look at a reset method PC.:)

Am I correct in saying that the ripple counters are being clocked from a 5MHz clock?

What is the source of the reset signal?

spec

Spec, the clock is 8MHz. There are 2 counters, each is 12bits, and they are cascaded together forming a 24bit counter. When the count reaches 159,743, the counters should be reset at the same time. That's all. The reset comes only from when the count reaches 159743, in binary that is 100110111111111111.

It seems the reset should be held for some time so that both counters can be reset.

The way I am resetting it now is that when the count reaches 159743, and the logic recognizes this, a HIGH appears at a flip flop, and then at the next clock edge, this value appears at the output of the flop, which is directly connected to the reset input of both counters. This isn't working and I don't know why because it seems to me the signal would reach both counters at the same time since the wires are the same length... :(
 

JimB

Super Moderator
Most Helpful Member
The problem is that I don't have schematics. I made it straight on the breadboard from my head as I went.
Then how is anyone who may try to help you, know how you have connected things together?

Circuit diagrams (schematics) are the language of electronics, without them how do you think that we communicate circuit ideas? Most of us do not have the power of telepathy.

JimB
 

PConst167

Member
Then how is anyone who may try to help you, know how you have connected things together?

Circuit diagrams (schematics) are the language of electronics, without them how do you think that we communicate circuit ideas? Most of us do not have the power of telepathy.

JimB

If you can't help or give general advice, then don't waste your time writing here. I don't need criticism about irrelevant things. Questions can be general. I am tired of people like you!!!

Many people can help and have helped. If you can't then don't try starting arguments like this so that other people follow your rotten writings.
 
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PConst167

Member
I will have a look at a reset method PC.:)

Am I correct in saying that the ripple counters are being clocked from a 5MHz clock?

What is the source of the reset signal?

spec

Guess what? The problem was not the reset afterall. I made a mistake in the circuit and when I used the last bit of the first counter as a clock into the second counter, I needed it to be inverted because the clock edge of the counters is negative! And I was using this inverted signal as the next bit on the new counter. This messed the counting up! Omg! :) It's all fixed now :)
 

JimB

Super Moderator
Most Helpful Member
If you can't help or give general advice, then don't waste your time writing here. I don't need criticism about irrelevant things. Questions can be general. I am tired of people like you!!!

Many people can help and have helped. If you can't then don't try starting arguments like this so that other people follow your rotten writings.
Well, that is me told!

I am not trying to start an argument, I am trying to point out how you can help others to help you.

JimB
 

PConst167

Member
Well, that is me told!

I am not trying to start an argument, I am trying to point out how you can help others to help you.

JimB

You don't always need schematics to answer questions though. There are many types of questions...
 

DerStrom8

Super Moderator
Most Helpful Member
Schematics always help. If you don't have schematics for something you've built, then draw some. Don't expect complete help if you can't provide complete information.
 
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