Thanks Eric. I was confident you'd have the answer!
I notice, too, that the Q1 output shows a glitch, and presumably that glitch is responsible for errors in subsequent stages.
Have downloaded your zip. I'm surprised, given the CD4060's popularity, that there isn't an 'official' Spice model for it available anywhere on the web (at least, none that I could find).
Playing with your sim, I idly tinkered with the TRIPDT value of the components; but that doesn't cure the problem. I see the problem is there when using the CD4024, too; so as you say it looks like a timing issue with all the CD4xxx family. Bummer. Anyone not aware of it will get dubious sim results.
I found the SPEED value of 2.0, for the gate which drives the Clk input of the 4020/4024, can be reduced to 1.5 and still cure the Q1 glitch while reducing the sim run-rate slightly.
Edit: It gets curiouser and curiouser (as Alice would say). Further play shows the SPEED =2 value doesn't always cure the problem, and that the SPEED can be left as 1.0 provided the timing cap (Tc) value is small (<~20n is ok, >~20n is not). I'm thinking the capacitive load on the Clk input of the 4020/4024 is the culprit. Using a voltage source for the clocking, or adding a series resistor (value dependent on the timing cap) between Tc and the Clk input fixes things, but the problem persists if a CMOS buffer (CD4050) between Tc and Clk is used!