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CD4026 counter reset issue

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qrper

Member
Gang..

this should be simple.

A basic two 4026 counter/display ICs counting pulses from a switch. When the output goes to 99 then 00, I take the carry out and trip another counter. that's working perfect.

now, when power is first applied to the circuit, the reset line (s) are pulsed high, and the counters reset to 00

okay, with me so far?

But when I push my reset button, that applies +12 to the reset pin, one display goes to 0 the second on to 1. If i hold the reset button in, both displays show '00' release the button and I get '10'

I've tried all sorts of interface to prevent switch bounce, such as a trigger from a 555, more debounce circuits that I can shake a stick at, and yet, they all seem to produce the same result——10 instead of 00.

This seems to simple, yet is confusing the snot out of me, so in one basic word----

"HELP!"

Qrper
 

MikeMl

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A schematic would help...
 

qrper

Member
okay, took a while to print, scan, and post. counter-1.jpg

the pin that says "LEDGND" goes to a transistor switch that turns off the display to save power.
 

Les Jones

Well-Known Member
Most Helpful Member
I think your problem is due to the fact that you also have the reset signal connected to the clock inhibit pin. I think the static state of the clock input to pin 1 of U10 is high which caused the high to low transition on the clock inhibit being seen as a clock signal to the first stage counter. (Incrementing it from 0 to 1.) The clock input on the second stage will be low so the level change on the clock inhibit pin does not cause it to increment. You need to show what provides the clock input to the first stage and give more information about what it is being used for so we can see if you can just invert the clock input signal.

Les.
 

qrper

Member
Interesting.... The circuit is quite common. screenshot_53.png
and this one shown is the one that I based my design around. Since all the inhibit pins are connected to the reset line, why does the second counter trip to one and not the others?

mike
 

eTech

Well-Known Member
Interesting.... The circuit is quite common. View attachment 98732
and this one shown is the one that I based my design around. Since all the inhibit pins are connected to the reset line, why does the second counter trip to one and not the others?

mike
les jones is right.

The difference is..... that circuit is not clocking the INH pin. It is connected to ground. In your other circuit, INH is clocked along with the Reset pin.
Instead, connect the INH pin to GND.
 

Les Jones

Well-Known Member
Most Helpful Member
Hi Mike,
I misunderstood the question. I thought it was the least significant digit that went to 1. You talk about two digits but you schematic shows three digits. It would be interesting to know how the third digit behaves. I still think the problem is related to the clock inhibit being connected to the reset line. What is the reason for connecting it this way ? I have just had another look at the timing diagrams on the data sheet and I now understand what is happening. In state 0 (The reset state.) the carry out pin is high. This is connected to the clock input of the next stage. This means that the counter now sees the 0 to 1 transition of the clock inhibit as a clock pulse. If you have to have the clock inhibit connected to the reset pin then the only solution I can see is to differentiate the carry out signal before connecting it to the clock input of the next stage. Connect the carry out to the clock of the next stage via a capacitor and connect the clock pin to ground via a resistor. The values will depend on how fast you are clocking the counter. I would try a 1 nF capacitor and a 10 k resistor. (I am assuming you are clocking it at less than a few tens of KHZ.)

Les.
 

qrper

Member
Les,

I can't tell you what the other display is doing until I get a second run of ICs in from mouser. I always buy more than I need, but you think I can find the damn things! They should be here tomorrow and I'll see what happens. The clocked input is quite slow, once every minute or so—it varies but never faster than a few cycles per SECOND.

So, what I'm hearing you say is divorce the clock inhibit from the reset line and place it (the clock inhibit) to ground.

I'll need to cut a few traces and some jumpers... Yup! Circuit is on a pcb. Things aways work on paper. Debugged on the protoboard, then other critters crop up when a pcb is made.

Mike
 

Les Jones

Well-Known Member
Most Helpful Member
Hi Mike,
To add the differentiator circuit you only need to make one etch cut (Between U10 carry out and U8 clock in.) Bridge the cut with the capacitor and solder a resistor from U8 clock in to ground. When you add the next 4026 you will have to do the same between U8 and the new 4026. It is probably worth doing this now to see if my theory is correct.

Les.
 

qrper

Member
Les,

divorce pin 5 of U10 from pin 1 of U8. Then insert a capacitor (.01, .1 ??) and a resistor (10K ?) from pin 1 of U8 to ground.

Before I go and start cutting traces, I'll put the ICs into sockets and lift the pins out of the sockets. I'll solder from pins to pin with some wire wrap wire.

But wondering why it's not working like it's shown in nearly every schematic I've seen on the 'net?

Mike
 

qrper

Member
les jones is right.

The difference is..... that circuit is not clocking the INH pin. It is connected to ground. In your other circuit, INH is clocked along with the Reset pin.
Instead, connect the INH pin to GND.
I'm a bit confused..

In my circuit I have the INH and RST going to ground via the 10K pull down.

The View attachment 98732 shows the INH and RST going to ground, without the resistor.

that's the issue? I should have the INH tied to ground, then the RST pins to ground via the 10K. Reset by applying +voltage to the reset pin and they'll be joy.

Mike
 

Les Jones

Well-Known Member
Most Helpful Member
Hi Mike,
The difference is that reset and clock inhibit are permanently connected to ground so there is no high to low transition on clock inhibit. If you look at the internal schematic of the 4026 (On the data sheet) you will see that the clock signal comes in through a schmitt buffer to an and gate and the clock inhibt comes in via a Schmitt inverter to an inverted input of the and gate. the inverted output of the and gate goes via an inverter to the clock input of the counter. When the clock input is high (As it will be as the carry out from the previous stage is high when it is in state 0 ) and the clock inhibit goes from high to low (When your reset button is released then the output of the and gate and inverters will go from low to high causing the counter to increment. With the resistor and capacitor the clock signal will only go high for a short pulse on the rising edge of the carry out signal.

Les.
 
Last edited:

Tony Stewart

Well-Known Member
Most Helpful Member
I recognize your problem as a race condition or now referred to as a 'metastable condition with asynchronous ripple clocks ( RCO) and async reset (switch)

The solution must be to sync the reset to clock inactive edge so that reset is removed on all chips 1/2 a clock cycle before the next active edge.

Want a 6 pin SMD D Flip ? http://ca.mouser.com/ProductDetail/...EpiMZZMvxP%2bvr8KwMwCQ0F1H8wvQHNPQqL8kv%2bGs=
just use inverted clock to sample switched input using schmitt trigger and RC cap to avoid all bounce unless your clock is > 20ms cycle or max bounce time. so the Reset state will always be at least 1 clo9ck cycle long and not just a bug's hair before one and have counters with different input clock thresholds ( forcing the race condition )
 

Les Jones

Well-Known Member
Most Helpful Member
Hi Tony,
The problem is not caused by a race condition. If you look at the clock and clock inhibit pins that are both active high (Clock low to high transition.) and swap over the inputs then the clock pin becomes a NOT clock inhibit (I.E. clock enable.) and the clock pin becomes a clock input that triggers on the high to low transition. The carry out signal is high from state 0 to state 4 and low from state 5 to state 9. As in state 0 carry out is high from the previous stage clock is high so the high to low transition of the clock inhibit increments the count when the reset button (Which is also connected to clock inhibit.) is RELEASED. The OP has not yet explained the reason for connecting the clock inhibit inputs with the reset inputs.

Les.
 

qrper

Member
I think your problem is due to the fact that you also have the reset signal connected to the clock inhibit pin. I think the static state of the clock input to pin 1 of U10 is high which caused the high to low transition on the clock inhibit being seen as a clock signal to the first stage counter. (Incrementing it from 0 to 1.) The clock input on the second stage will be low so the level change on the clock inhibit pin does not cause it to increment. You need to show what provides the clock input to the first stage and give more information about what it is being used for so we can see if you can just invert the clock input signal.

Les.
Les, I need to buy you a beer!

I removed the counter chips from the pcb, installed sockets, lifted pin 2 out of the socket. Connected all the pin twos together, then ground.

when I press the reset button, everything now goes to zero.

Thanks a bunch..

mike
 
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