Can SOT23 transistor dissipate 175mW when on minimal size pads on the PCB?

[Flyback]

What we have not been told is the condition which this transistor has to detect.

my post #10 shows what's going on......the PNP(s) is there to give detection of an open LED load.....the collector of Q2 will go low, if either or both of the LED loads goes open.

The resistor is 100R, 0603, but we can maybe change this to say 2512 to give good derating for the 0.175^2*10 = 306mW that it would be dissipating

 

[JimB]

my post #10 shows what's going on......the PNP(s) is there to give detection of an open LED load

OK, that is good, I thought that I had seen that somewhere.

The resistor is 100R, 0603, but we can maybe change this to say 2512 to give good derating for the 0.175^2*10 = 306mW that it would be dissipating

Yes, that is the sort of thing I had in mind.

Maybe the resistor could go a bit lower, and reduce the dissipation even more.
A 6.8R would give about 1.2v to turn on the transistor, and the dissipation would be 210mW.
Even better?

JimB

 

[crutschow]

Do you know how to get LTspice to run the simulation with the CPH3105 model? ( I downloaded it from onsemi.com, but can't get LTspice to use it....it gives error message *Could not open library file "CPH3105"*

I don't understand why it can't open it, as its in the schematic, as may be seen in the attached.?

Post your .asc file.

 

[Flyback]

thanks, yes that 210mW sounds better.
I bet they wont want to do it though........as a final "nail in the coffin" for the original circuit of post #1 and #10, would you say that the inrush current into the 22uF capacitor at start up could possible damage the CPH3105 PNP?..... if so then this will really add weight to the campaign to get this circuit changed.

 

[Flyback]

Post your .asc file.

...thanks, just done it, I had a .ENDL statement in the .model statement...which I had to comment out....ive obscured my original question..sorry I didn't get to this point sooner

 

[crutschow]

...thanks, just done it, I had a .ENDL statement in the .model statement...which I had to comment out....ive obscured my original question..sorry I didn't get to this point sooner

So you posted the file? Where?

 

[Flyback]

here is the ltspice sim of it

 

[JimB]

Tell me one more thing, when asking questions like this, why do you set off only giving half the information?

A schematic is given in post#1, but then in post #10 the little added detail is given that the transistor also provides the supply to another identical stage.
This may affect the selection of a value for R2.

Also in the schematic of #10, have you considered that when load 1 fails to 0mA, the supply is removed for load 2 ?

JimB

 

[Flyback]

Also in the schematic of #10, have you considered that when load 1 fails to 0mA, the supply is removed for load 2 ?

yes that's not a problem....we want "one off all off"operation, so that the upstream current monitor knows the fogs or rev lights are gone.

....if posters could have given a bad bill of health to the schem of #1, then I would not have needed to post any further info.....it would have been "goodnight Vienna" to the circuit. I simply included the #10 schem for interest..........
The vce is surely very low(?)....and in any case, if #1 schem was a no-no, then #10 would definitely been a no-no.

However, there seems some consencus that #1 mightn't be that bad, but would best be changed anyway.

 

[ronv]

Yep, my bad. It is always on. The cap, depending on it's esr could be an owie.

 

[Flyback]

**broken link removed**
the 22uF cap is EEHZC1V220R, as above datasheet.

..."owie" I tend to agree with...I would have thought that inrush currents through a BE diode is a big no no?

Woops....though tan delta s 0.12...therefore ESR = Xc*tan delta = 7.23 Ohms....oh maybe not that bad inrush then.....

 

[crutschow]

According to the simulation, Q1 dissipates 149.7mW and Q2 dissipates 145.5mW (press Alt when the cursor is over the transistor to plot the power).

If you change R2 and R3 to 5Ω, then the power dissipated drops to 20.5mW and 17.7mW respectively. The base current is still way more than sufficient at >21mA for both transistors.

 

[Flyback]

JimB has gone for 6R8, to give 1v2 minimum across the be junction of CPH3105....so if the resistor is to be downsized...its 6R8 or bigger...due to the pesky 1v2 max vbe

 

[crutschow]

6.8Ω works for me. Even 10Ω reduces the typical transistor power to <80mW for both transistors.

 

[ronv]

I still worry about the current charging the cap. When I run your simulation with a similar cap I see 7 amps. Maybe it's ok, I've just had some bad experiences.......

 

[Flyback]

you see 7 amps?..but v(supply) is 12v,and esr is 7 ohms

 

[ronv]

At power on.

 

[crutschow]

you see 7 amps?..but v(supply) is 12v,and esr is 7 ohms

The simulation circuit has an ESR for C1 of 0.1 ohm.

 

[Flyback]

my apologies, I forgot to add the 7 ohms esr into the caps in the ltspice simulation

 

[ronv]

I plugged in a cap with .8 ohms for a spec.