Can not get common source amplifier working in simulations

#24 in my answer has a gain of ~10

You still don't get it.

Vt = Vgs(th) has a tolerance at say 1mA of 33% to 50% like the QS8K2 which is 0.5 to 1.5V. Even using 1% resistors you have to guess what batch of FETs you have to make it work. You'll never achieve an accuracy of 10% with the Vt tolerance. It is more likely you get attenuation at extreme Vt values. Design Failed.

I got a gain 18 in Falstad open loop by choosing beta=22, RdsOn = 55 mOhm, Vt= 1.0V (mid-range)

But by choosing negative feedback, you can achieve < 2% accuracy by design even with +/-50% tolerance on Vt.

Tony Stewart said:

You still don't get it.

Vt = Vgs(th) has a tolerance at say 1mA of 33% to 50% like the QS8K2 which is 0.5 to 1.5V. Even using 1% resistors you have to guess what batch of FETs you have to make it work. You'll never achieve an accuracy of 10% with the Vt tolerance.

I got a gain 18 in Falstad open loop by choosing beta=22, RdsOn = 55 mOhm, Vt= 1.0V (mid-range)

But by choosing negative feedback, you can achieve < 2% accuracy by design even with +/-50% tolerance on Vt.

Click to expand...

Yes but the required circuit was the CS amplifier with resistor load. In the pdf diode connected load and triode load were added. I am sure no one would use that setup to make useless amplifiers on silicon when it can be easily improved like you did. When class progress they will want more complex and hopefully usefull circuits to be simulated.
Aren't resistors that are made on silicon suck because they have even worse tolerances than Vt without expensive stuff like laser trimming? Point of the class I am taking is learning to design analog integrated circuits like Op Amps produced on silicon. It is my fault for missleading because I did't know what to do.
My original tests didn't work on cadence because I failed to configure input voltage supply. I can try your circuit again now.

Gain near 8 , manually tuned with Vdd = 2.5V


Rev 1 https://tinyurl.com/2c3lwyo9

Rev 2 proof of Vgs used https://tinyurl.com/26lyemu8

Probability of this design working with 50% tolerance and gain of 8 is < 10% i.e. Vt must be nominal with 5% otherwise clipping or zero gain if exceeded.

I got 100 times gain with folded cascode. Maybe I can replace those DC supplies with current mirrors to save myself from Vt inconsistencies in production but I don't care that for this simulations. Values are extremely sensitive for changes and gain immediately drops even if length of the bottom mosfet is 5nm longer than it is.


There is something with this mosfet model that causes around 20uA to give the best gain. No more no less will drop the maximum achievable gain.

The very dynamic impedance ratios of cascode need to be buffered and are unable to be reliable without feedback due to thermal effects.

Here's a practical R&D paper with Monte Carlo analysis on a cascode CS FET amp.

from researchgate.net

The frequency response of this amplifier is limited. This is the main drawback. The amplified output voltage can be applied to either a common-drain circuit ( voltage follower) or a common-gate circuit (current follower).
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I also fixed the circuit and changed the simulation "tran" so we can see the waveform properly: