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Can not get common source amplifier working in simulations

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Fluffyboii

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I tried for an hour or so to make a mosfet amplifier in LTspice but I never got gain more than 1 no matter what values I used for bias resistors ,drain resistor, source resistor. If I recall correct gain should be something around -drain resistance/source resistance but nope it just doesn't work.

I need to make a amplifier with 8V/V gain with maximum 2.5Vdrain. I will calculate the values with the boring old fashioned way but it seemed odd that I couldn't get anything working with ballpark values. Cadence also had the same issue so I am assuming I forgot something important. (I tried using more Vd in Cadence later, it didn't help)
 

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You still don't get it.

Vt = Vgs(th) has a tolerance at say 1mA of 33% to 50% like the QS8K2 which is 0.5 to 1.5V. Even using 1% resistors you have to guess what batch of FETs you have to make it work. You'll never achieve an accuracy of 10% with the Vt tolerance. It is more likely you get attenuation at extreme Vt values. Design Failed.

I got a gain 18 in Falstad open loop by choosing beta=22, RdsOn = 55 mOhm, Vt= 1.0V (mid-range)

But by choosing negative feedback, you can achieve < 2% accuracy by design even with +/-50% tolerance on Vt.

 
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You still don't get it.

Vt = Vgs(th) has a tolerance at say 1mA of 33% to 50% like the QS8K2 which is 0.5 to 1.5V. Even using 1% resistors you have to guess what batch of FETs you have to make it work. You'll never achieve an accuracy of 10% with the Vt tolerance.

I got a gain 18 in Falstad open loop by choosing beta=22, RdsOn = 55 mOhm, Vt= 1.0V (mid-range)

But by choosing negative feedback, you can achieve < 2% accuracy by design even with +/-50% tolerance on Vt.
Yes but the required circuit was the CS amplifier with resistor load. In the pdf diode connected load and triode load were added. I am sure no one would use that setup to make useless amplifiers on silicon when it can be easily improved like you did. When class progress they will want more complex and hopefully usefull circuits to be simulated.
Aren't resistors that are made on silicon suck because they have even worse tolerances than Vt without expensive stuff like laser trimming? Point of the class I am taking is learning to design analog integrated circuits like Op Amps produced on silicon. It is my fault for missleading because I did't know what to do.
My original tests didn't work on cadence because I failed to configure input voltage supply. I can try your circuit again now.
 
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1669389532354.png

I got 100 times gain with folded cascode. Maybe I can replace those DC supplies with current mirrors to save myself from Vt inconsistencies in production but I don't care that for this simulations. Values are extremely sensitive for changes and gain immediately drops even if length of the bottom mosfet is 5nm longer than it is.
1669389636321.png


There is something with this mosfet model that causes around 20uA to give the best gain. No more no less will drop the maximum achievable gain.
 
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The very dynamic impedance ratios of cascode need to be buffered and are unable to be reliable without feedback due to thermal effects.
 
I also fixed the circuit and changed the simulation "tran" so we can see the waveform properly:
 

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