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can anyone help me simplify this?

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hi, the res/cap circuit is something like this?

but for U6A and U5A, why i couldnt replace them with a NAND gate? the output waveform would be neither high nor low if i used NAND insteed.

hi,
The top of the 10K has to go to the +V, so that on power up the FF is cleared.
You will have to use an OR gate to combine the output of the Res/Cap and the logic Clear.

You could use a NAND for U6A/5A, but as a designer you should consider the total ic count.!

EDIT:
Look at this image, its not been fully checked, but should suggest a solution.
 

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