ripple counters
A binary ripple counter consists of a chain of flip-flops, with each flip-flop output (the q's) serving as the clock for the next F/F in the chain. The name comes from the effect of the input clock as it "ripples" down through the chain (think of a row of dominoes falling down, it's a pretty good analogy). The first F/F in the chain is the least significant bit (LSB) of the binary counter, the last is the MSB.
This type of counter is mostly seen in standard logic parts, like the CD4020/4040/4060 or 74xx393. Ripple counters were popular in the early days of digital logic, since they didn't require much in the way of combinatorial logic. You'll also come across the term "synchronous binary counter". In synchronous counters, all of the outputs (q's) change state on the same clock edge. Synchronous counters have largely replaced ripple counters in FPGAs and other programmable logic architectures, due to their lower propagation delays and higher noise immunity. They do require considerably more combinatorial logic to make. It's never been a problem for the "sum-of-product" architecture you find in PLDs, and nowadays most FPGAs include "fast-carry-logic" as an aid to building synchronous counters.
Take a look at the internals of a 74HC393 (dual 4-bit binary ripple counter) versus a 74HC4520 (dual 4-bit binary synchronous counter) to get an idea of the difference between the two types of counters.
btw, a 14-bit binary counter will divide an input signal by 2^14 (16384). That's why you get a 1/2 second output from a CD4060 and a 32.768Khz crystal.