Algorithmic State Machine Method

[S1nGh]

Hello Everybody....Need urgent help....I am trying to understand the above topic for my test on Tuesday Next Week....

Would Anybody please explain to me how I would do the below using ASM method:

"A circuit is required to control an ADC (Analogue to Digital Converter) by
asserting a control signal called SC ("Start Conversion") and waiting for a
status signal called EOC ("End Of Conversion") to go high. You may deassert
SC when you receive a high on the EOC status signal whereupon
EOC will drop low within a microsecond. The circuit should take eight
readings at 1 second intervals and output an average value to a DAC
(Digital to Analogue Convertor). The DAC requires a STROBE control to
be asserted after the data; you should keep STROBE asserted until the
DAC asserts its ACK status signal to confirm it has accepted the data.
You can then drop the STROBE signal and the ACK status line will drop
low within a microsecond. Assume a system clock of 1MHz is available
and also a module called DIV-1M that divides the system clock rate by
one million."

Even A rough Block diagram would be helpful...
Thanks

 

[ericgibbs]

hi,
Look at the diagrams and explanations in these links.

Information Theory and Creationism: Algorithmic Information Theory (Chaitin, Solomonoff & Kolmogorov)
**broken link removed**
**broken link removed**

 

[S1nGh]

hi,
Look at the diagrams and explanations in these links.

Information Theory and Creationism: Algorithmic Information Theory (Chaitin, Solomonoff & Kolmogorov)
**broken link removed**
**broken link removed**

Thanks Dude!!

I will try and absorb

 

[S1nGh]

hi,
Look at the diagrams and explanations in these links.

Information Theory and Creationism: Algorithmic Information Theory (Chaitin, Solomonoff & Kolmogorov)
Back to Tools
Technology behind the software

I tried the above sir, but still wasn't able to figure out how to start the design....

I understand the basic ASM method but am not able to design the ADC circuit...

KJ

 

[crutschow]

Have you drawn a state (flow) diagram of the state machine states? That's the first step in designing a state machine.

 

[S1nGh]

Have you drawn a state (flow) diagram of the state machine states? That's the first step in designing a state machine.

I know the first step is a flowchart....but not able to figure it out....would you might telling me whats happining the above question so I can draw a flowchart and post it up here for you to check....

 

[3v0]

Do you understand what a state machine is and how a process can be broken down into a set of states.

 

[S1nGh]

Yes SIR I do....I have drawn a state machine before something like this
https://www.metacase.com/images/uml20statemachine.png

But my issue is with the above problem I posted in the first post......
I am not sure how to start as it says Start Conversation which means the begainning in the flowchart and End of Conversation meaning the end of flowchart....but I cannot visualise where the rest of the content go....

Hope ya understand.....

KJ

 

[ericgibbs]

Yes SIR I do....I have drawn a state machine before something like this
http://www.metacase.com/images/uml20statemachine.png

But my issue is with the above problem I posted in the first post......
I am not sure how to start as it says Start Conversation which means the begainning in the flowchart and End of Conversation meaning the end of flowchart....but I cannot visualise where the rest of the content go....

Hope ya understand.....

KJ

Hi,
Look here:

**broken link removed**
Analog to Digital converter (ADC) interfacing with Microcontrollers tutorial: Introduction : 8051 Microcontroller Projects AVR PIC Projects Tutorials Ebooks Libraries codes

The SOC and EOC are not the start and end of the flow chart they are 'commands' for the ADC and DAC modules within the flowchart structure.

 

[S1nGh]

Hi,
Look here:

**broken link removed**
Analog to Digital converter (ADC) interfacing with Microcontrollers tutorial: Introduction : 8051 Microcontroller Projects AVR PIC Projects Tutorials Ebooks Libraries codes

The SOC and EOC are not the start and end of the flow chart they are 'commands' for the ADC and DAC modules within the flowchart structure.

Thanks dude for help......
I feel much better now.... as I have my exam tomorrow....I guess
have to burn my midnight lamp.....

Anways will let ya know if i get stuck....

KJ

 

[ericgibbs]

Thanks dude for help......
I feel much better now.... as I have my exam tomorrow....I guess
have to burn my midnight lamp.....

Anways will let ya know if i get stuck....

KJ

hi,
I would recommend that you paste the text description of the project into a text document.
Break it down into bite sized pieces, the flow chart will evolve as you expand the text.

Do you follow that.?

"A circuit is required to control an ADC
by asserting a control signal called SC ("Start Conversion")


and waiting for a status signal called EOC ("End Of Conversion") to go high


You may deassert SC when you receive a high on the EOC status signal whereupon EOC will drop low within a microsecond


The circuit should take eight readings at 1 second intervals and output an average value to a DAC


The DAC requires a STROBE controlto be asserted after the data;

you should keep STROBE asserted until theDAC asserts its ACK status signal to confirm it has accepted the data.

You can then drop the STROBE signal and the ACK status line will drop low within a microsecond.

Assume a system clock of 1MHz is available

and also a module called DIV-1M that divides the system clock rate by one million."

 

[S1nGh]

hi,
I would recommend that you paste the text description of the project into a text document.
Break it down into bite sized pieces, the flow chart will evolve as you expand the text.

Do you follow that.?

Yes Sir i do.....this is a very good technique

 

[S1nGh]

Right.....

Take it Asserting means - active state and
De-asserting means - Inactive state.

So should I start something like this:

Start
|
start Conversation......etc

KJ

 

[ericgibbs]

Right.....

Take it Asserting means - active state and
Sometimes called Enable

De-asserting means - Inactive state.
Sometimes called Disable
So should I start something like this:

Start
|
start Conversation......etc

KJ

hi,
Consider you have to initialise:
the [8] counter
clear the adcvalue averaging buffer
clear any other buffers
........................... you must do this routine every time you start a new average of 8 adc samples

Now Start the Conversion by enabling the SOC flag, wait while the EOC flag is valid, now read the adc value.... do this 8 times forming a SUM of the 8 readings, with a total wait state of 1 second per reading. [ 8secs total time/avg]

When all 8 have been saved, divide by 8 to give the ADC average.

Now do the DAC sequence, using the ADC average as an input.

And keep repeating