The way I'm reading the above is that 1.0uS is a good period for TAD. I'm running at 32MHz and assume that there's a missing row of Fosc/32 where my time will be 1uS.

To further confuse the matter, the register where you set this value seems to have a typo,

Surely those (divisor) values should be halving each row and Fosc/124 is a typo and should be Fosc/32?

Is there another document that describes this?

Thanks for any comment.

Mike.