Hi guys, I wish u r all okay. This project is a university project and I don’t know how to start with all this............ :shock: . I hope one of u could solve it. The most important thing is the circuit diagram. however, there is a simulation part which I can solve it if I have the diagram :
The project stat that:::
It is required to design a discrete common emitter common collector cascade amplifier stage for lower 3-dB frequency f L less than or equal to 100 Hz and an upper 3-dB frequency f H greater than or equal to 4 MHz. the typical transistor parameters at room temperature are : Bo = 100, Cµ = 8pF and Cpi= 30pF. For this particular design, we also have the following specification: the supply voltage is 12 v, the source resistance Rs = 1K ohm; and the load resistance is RL = 10Kohm;. Neglect the effect of the output and base spreading resistance. The operating point has to be reasonably stable for normal environmental temperature changes and interchangeability of transistor and should allow for maximum signal swing.
:shock: :shock: :shock: :shock:
the original pdf file for this project is included
Thanks
:roll:
The project stat that:::
It is required to design a discrete common emitter common collector cascade amplifier stage for lower 3-dB frequency f L less than or equal to 100 Hz and an upper 3-dB frequency f H greater than or equal to 4 MHz. the typical transistor parameters at room temperature are : Bo = 100, Cµ = 8pF and Cpi= 30pF. For this particular design, we also have the following specification: the supply voltage is 12 v, the source resistance Rs = 1K ohm; and the load resistance is RL = 10Kohm;. Neglect the effect of the output and base spreading resistance. The operating point has to be reasonably stable for normal environmental temperature changes and interchangeability of transistor and should allow for maximum signal swing.
:shock: :shock: :shock: :shock:
the original pdf file for this project is included
Thanks
:roll: