89c51 interfaced with 6264

[tpramanhyd]

i have 89c51 hooked with adress decoder 138.
My issues is i am not able to write or read data from address location f000h
(as per my schematics f000 should refere to 6264, i checked with chip select signal output of the decoder, write and read pulses all of them tranisit b/w high and low as expected).
But i am not able to send or receive data from 6264. I use a serial link for display of data onto pc.

 

[masud58]

can send scametic diagram? i have many project with at89c51 and 62256 ram. keyboard based moving display, exchenge rate board, computer to moving display board. i use simulator proteus, keil, bascom. but iam working with pic

thanks

 

[masud58]

dont worry

can u send scametic diagram? i have many project with at89c51 and 62256 ram. keyboard based moving display, exchenge rate board, computer to moving display board. i use simulator proteus, keil, bascom. but iam working with pic

thanks

masud
dhaka

 

[tpramanhyd]

i dont have a soft copy of schematic but to solve my issue i guess i've given required information.

 

[masud58]

look at this

**broken link removed**

 

[Papabravo]

i have 89c51 hooked with adress decoder 138.
My issues is i am not able to write or read data from address location f000h
(as per my schematics f000 should refere to 6264, i checked with chip select signal output of the decoder, write and read pulses all of them tranisit b/w high and low as expected).
But i am not able to send or receive data from 6264. I use a serial link for display of data onto pc.

I think a 6264 is an 8K by 8 bit part. It should occupy the space from 0xE000 to 0xFFFF, is this correct? The 138 decoder output goes to the CS-bar input on the 6264, RD* goes to OE-bar on the 6264, and WR* goes to WE on the 6264. You remembered to write 0xFF to the P2 and P0 data registers to enable the altenate function and you have correctly demultiplexed the Address/Data bus on P0 with a transparent latch controlled by ALE.

The only thing left is access time. What speed is the 89C51 running at and how long are the RD* and WR* strobes. Look at the definition of the AUX or AUX1 registers for a streched version of RD* and WR* that takes 30 clock cycles instead of six clock cycles. Check the 6264 data sheet for setup time, hold time and access time requirements. Also make sure that you enable ALE to be active.

 

[tpramanhyd]

thnks for the information i checked with the access time of 6264 which was less than required n it solved the issue.

 

[abilowo]

i have many project with at89c51 and 62256 ram.

can you send me the schematics?
i'm building the system that control ADC, save the data at 62256 RAM, then send it through serial port to pc. but i still confuse with the connection between micro (i used at89s51), 62256, ADC data, and buffer 74xx573.

thanks for helping...

 

[masud58]

test

look at my design

 

[abilowo]

thanks. i'll learn it.

thank you...