Sorry, I dont understand why i need a latch and 8 count detector circuit? is it to drive the clock because i was thinking of using a astable pulsing at very high freq for the clock.
Sorry, I dont understand why i need a latch and 8 count detector circuit? is it to drive the clock because i was thinking of using a astable pulsing at very high freq for the clock.
Basically i want to detect 5 spikes from a pulse generator, hence 5 counts and when the counter counters upto 5, sends 5 to the shift reg. the shift reg will transmit the 5 serially, than after some more circuit transmits the signal wirelessly. upon retreiving the 5, a SIPO shift register will convert the 5 back to parallel to display on a display.
Basically i want to detect 5 spikes from a pulse generator, hence 5 counts and when the counter counters upto 5, sends 5 to the shift reg. the shift reg will transmit the 5 serially, than after some more circuit transmits the signal wirelessly. upon retreiving the 5, a SIPO shift register will convert the 5 back to parallel to display on a display.
The problem will be once the 8 bits containing the '5' data are shifted out, the S/R will continue to shift out LOW bits until the next '5' is PLOAD.
How will your remote SIPO keep in sync, it will keep receiving low bits in between the '5's group.
Keeping master and slave clocks in sync is close to impossible with regular components.
An idea would be to connect the 3 used top bits high, so that 11100101 is transmitted, the three 1's could easily act a sync pulse.
In fact its always a '5' send a string of 111111111 as meaning a 5 count with just 0000000's in between, detect the 1's at the remote.?
You would use a monostable and gates at the remote end.
Each '1' would trigger the mono, which would have an ON period of just over the period of '1' bit.
If a 2nd '1' was received while the mono was timing, a gate would be used for the incoming '1's and the mono output.
When the mono and and the next '1' are High, thats the sync pulse.