hi,
If I am reading your circuit correctly, you dont appear to be using the LOAD pin and the SERout is connected to 0V.??
You are not showing the clock circuit.?
On the '5' count you need a LOAD pulse to the S/R, then 8 clock pulses to shift out the '5' [bits] on the SERout pin.
EDIT:
I see on the datasheet that DS is Serial Data input and Q7 is the Serial Data output, so your 0V to DS is correct, its just the PLOAD thats required and the 8 clock shift pulses.
The Serial out is connected to a SIPO shift registers. I was told that the load pin should be HIGH to enable the count operation. It has to High for shifting but pulsed Low for Loading the '5'
The clock to the shift reg should be a clock voltage, pulsing at 100khz You need to allow 8 clock pulses after the LOAD has pulsed Low, then stop them to the S/R
The counter is not clock, it counts at different times.
ok,
As the count is always '5' why not hardwire the '5' bits on the parallel input and use gates to detect the 5th count of the 193 and use that as a PLOAD pulse.
You still need the 8 clock pulses to clock out the S/R.
Yes, but dont forget to connect the other 4 input pins to 0V, because when disconnected on a 165 the will assume a high.
By inverting the PLOAD from the NAND gate, using another NAND or INVERT you could auto RESET the counter
Do you mean the PLOAD or the 193 RESET.???
At the 5th count PLoad will go low and load the '5', to enable the 165 to shift the PL must go high, thats why I suggested the auto Reset of the 193.
By clearing the 193 count, the PL will go high, enabling the shifting.
You may find that you will have to add a short delay in the RESET by adding a res/cap in the RESET line.
Do you follow.?
When you have that part working, you need a LATCH, you can use two NAND gates.
The LATCH would be set when the 165 is loaded with the NAND gate '5' detect circuit.
With latch set, gate clock pulses into the 165, to shift out all 8 bits, when the last bit is detected reset the latch.
You will need a 8 count detector circuit.
OK