I think the datasheet may also give this for you.....as well as the babani book on 555 timers.
You can mess about with the 555 in the free ltspice simulator till you get 50%
I just built one of those and found that the duty cycle is not quite 50%, especially at a Vcc of 5V. With Vcc=12v, it comes a bit closer, but still no better than 50% +-3%. The timing resistor was ~40K. I assume that the asymmetry is due to a slight imbalance in the PNP/NPN pull-up/pull-down in the output stage that drives pin 3. Might be better if the timing resistor was >100K, but haven't tried it.
I think the datasheet may also give this for you.....as well as the babani book on 555 timers.
You can mess about with the 555 in the free ltspice simulator till you get 50%
The 555 behavioral model in the LTSpice library is too perfect to show behavior I talk about in post #4, above. There is a better 555 model on the Yahoo Group that is more realistic...
Just use a divide-by-two flip-flop after the 555 and you won't have to tweak it to get an exact 50% duty-cycle.
Any 555 astable circuit will always be a little off from exactly 50%.
Use an edge-triggered toggle flip-flop. The 555 asymmetry could be anything from 1% to 99%; it matters not since the flip-flop changes state only on either the rising edge or falling edge (depends on the specific flip-flop). The 555 has to run at twice the frequency of the resulting (perfectly symmetrical) square wave out of the flip-flop.