It is problematic to tie the TRIG input low on a 555, since the inputs are level triggered and it will likely not time out (output stays high).
Below is the LTspice simulation of a 555 circuit which avoids that problem by connecting the TRIG input to the charging capacitor.
The capacitor voltage is initially zero, so when circuit power is first applied (yellow trace), the 555 TRIG input is triggered, the OUTput goes high (blue trace), and the capacitor starts charging (red trace).
This is similar to an astable configuration, but with no DIS connection, so when the capacitor charges to the THRS voltage, the 555 internal latch is reset to the low OUTput state (at about the 16.7s point on the simulation), but the capacitor isn't discharged.
The THRS and TRIG inputs thus stay high, which maintains the 555 internal latch in the low state, so it doesn't continue pulsing.
The result is a single 15 second output pulse (as determined by R2-C1) upon the application of power, and then the output stays low until the power is reset.
D1 discharges C1 when the power is removed.