555 output

[John Murdock]

Regarding the 555 IC, I seem to have a gap in my knowledge on it regarding the output signal for the monostable and astable. Of course the monostable is a 'one shot' while astable goes on and off.

My question is what determines the time period for which the signal is high and the time for which it is low? is it the RC network of the capacitor and resistors and if so, if i was told to sketch the signal as if it had a probe right on pin 3 how would i go about doing that. ( by that I mean sketching this for a 555s output for both monostable and astable: )

 

[MikeMl]

The 555 (when wired as a monostable) triggers (OUTPUT goes high, and timing starts) during the down-going edge of the TRIGGER. To get the PERIOD T implied by R*C, the TRIGGER pulse must be shorter than T. If TRIGGER is longer than T, then T lasts until TRIGGER goes back high beyond its natural timing interval.

The TRIGGER input usually has a DC blocking (coupling) capacitor with a resistor pull-up to make it truly "edge triggered" instead of "level triggered".

 

[ericgibbs]

hi John,
Look at page #8 of the 555 App PDF.

E

 

[John Murdock]

hi John,
Look at page #8 of the 555 App PDF.

E

What exactly is Rb in this picture, C is the capacitor and Ra is the resistor, Rb? I believe it is meant to show a resistor.

Just found this after using your link to lead me in the right direction:


**broken link removed** It has a more ' I'm an idiot explain it to me' stance.

in case any newbies like me are asking the same questions.

 

[JimB]

Yes it is the resistors and capacitor which define the periods.

This scabby old datasheet from the 1970s shows quite well how to calculate for an astable.

JimB

 

[granddad]

Doesn't the output (3) need a load to give a waveform ?

 

[MikeMl]

Doesn't the output (3) need a load to give a waveform ?

No. It has active pull-up and active pull-down. You are thinking of some TTL one-shots.

 

[John Murdock]

The 555 (when wired as a monostable) triggers (OUTPUT goes high, and timing starts) during the down-going edge of the TRIGGER. To get the PERIOD T implied by R*C, the TRIGGER pulse must be shorter than T. If TRIGGER is longer than T, then T lasts until TRIGGER goes back high beyond its natural timing interval.

The TRIGGER input usually has a DC blocking (coupling) capacitor with a resistor pull-up to make it truly "edge triggered" instead of "level triggered".

In Regards to the astable, why is their high and low timing is it because it is neither connected directly to top and bottom rail due to having two different resistors?

And when drawing the output signal for an astable does one use the mark space ratio?

 

[AnalogKid]

View attachment 98597
What exactly is Rb in this picture, C is the capacitor and Ra is the resistor, Rb? I believe it is meant to show a resistor.

It sorta does. If you keep the same resistor designations as in the astable circuit, then for a monostable Rb is zero ohms.

ak

 

[ericgibbs]

hi John,
Look at this ETO Tool
https://www.electro-tech-online.com/tools/IC555V2T1.php

Also checkout the other 555 Tools.
E

 

[MikeMl]

In Regards to the astable, why is their high and low timing is it because it is neither connected directly to top and bottom rail due to having two different resistors?

And when drawing the output signal for an astable does one use the mark space ratio?

Look at this sim. The timing capacitor charges through R1+R2, but discharges only through R1 because the "discharge" pin switches to very near ground at the same time V(out) is low. Note that the first charge phase is longer than all the others, because the timing capacitor starts out at zero V, while on subsequent cycles, it is cycling from 1/3Vcc (4V) to 2/3Vcc (8V) when the 555 is powered from 12V.

After you understand this, you will notice that is very hard to get a mark (high) to space (low) ratio that is less than one...