CLRF CCP1CON ; CCP Module is off
CLRF TMR2 ; Clear Timer2
MOVLW 0x7F ;
MOVWF PR2 ;
MOVLW 0x1F ;
MOVWF CCPR1L ; Duty Cycle is 25% of PWM Period
CLRF INTCON ; Disable interrupts and clear T0IF
BSF STATUS, RP0 ; Bank1
BCF TRISC, PWM1 ; Make pin output
CLRF PIE1 ; Disable peripheral interrupts
BCF STATUS, RP0 ; Bank0
CLRF PIR1 ; Clear peripheral interrupts Flags
MOVLW 0x2C ; PWM mode, 2 LSbs of Duty cycle = 10
MOVWF CCP1CON ;
BSF T2CON, TMR2ON ; Timer2 starts to increment
;
; The CCP1 interrupt is disabled,
; do polling on the TMR2 Interrupt flag bit
;
PWM_Period_Match
BTFSS PIR1, TMR2IF
GOTO PWM_Period_Match
;
; Update this PWM period and the following PWM Duty cycle
;
BCF PIR1, TMR2IF