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100uF Ceramics - Capacitance at higher voltage

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ACharnley

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Hi all,

I have a small PCB and a small case which mitigates using small smd capacitors to smooth a low frequency AC input. Testing has shown the buck chip ideally needs 470uF @ 25v to lower the ripple enough for stability.

In addition, high reliability and long life is paramount and the capacitors will get a hard work out (low frequency SIN, 0-21V AC) thus I investigated using newer high capacitance ceramics. After prototyping with some 1812 100uF/25V ceramics which worked (but measured 75-80uF) I went ahead and purchased 6,000 100uF 25V 1210 ceramics from TDK in Japan at $0.12 each (I was wary how they could fit such capacitance in such a small volume but the product code checked out and it's TDK...).

Then came the catch, when I measure these they are 47-60uF, which mitigates using double the amount. This is not a problem room wise but it does add additional cost to each product. This checked out on the PCB, if I use 6 it's not stable, but 12 is ok. The buck prefers low ESR and these are X7R.

I went back to the supplier and she says my multimeter is wrong. Perhaps. If I measure any electrolytic it is 100% accurate. If I measure a .001uF ceramic it gets the value to within 20%. It doesn't explain why the PCB requires double and the multimeter states the capacitance as half.

She said to use a multimeter that allows switching the charge voltage to a 1v level, which apparently (can't test with mine) gives a reading closer to the 100uF. I explained that the reason I bought 25v rated ceramics was I expected the capacitance not to change that significantly (half!) as the voltage rises. The typical PCB voltage is ~7V and they've lost half at that point.

Could you advise if there's anything else I have overlooked?
 
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You can try the RC discharge test.
Charge the cap up to various voltages with a power supply and then observe the discharge to 1 time-constant (36.8% of the initial voltage) with a digital voltmeter. If you make the total resistance across the capacitor 1 Megohm, the time-constant will be about 100 seconds which should be a sufficiently long time to fairly accurately note the 0.368 point.
If you connect a 1.11 Megohm resistor across the capacitor then that, in conjunction with the typical 10 Megohm meter resistance, will give an equivalent 1 Megohm capacitor load.
That should show if there's a significant difference in capacitance with voltage.

You could also check at the 1/2 time-constant point (60.7% of the initial voltage).
 
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Done (1.11mOhm), and oh no...

100uF 25v electrolytic

15.04v -> 5.53v = 1.35
6.57v -> 2.41v = 1.40

"100uf 25v" ceramic

15.04v -> 5.53v = 0.13
6.57v -> 2.41v = 0.36
2.07v -> 0.76v = 1.28
 
Could it be that these have very high leakage? The seller is adamant they are real and in spec.

edit: leakage seems ok (certainly not that much in 100s)
 
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I just tested a larger 1812 100uF 25v ceramic (from the prototype) and got;

15.04v -> 5.53v = 0.08
6.57v -> 2.41v = 0.21
2.07v -> 5.53v = 1.00

So either I'm missing something or none of these ceramics are anything like true capacitance unless they're charged at 1V. Possibly they are not 25v rated (more like 2V!)?
 
We are missing the link to the specs and characteristics and test methods.

Your design may be flawed with conflicting requirements for small size, MTBF, low ESr,,high C

Normally holdup time for C is 1 or 2 cycles up to 20 cycles for low ripple V. Since your switching time is presumeably short but the load is DC to low f, you must examine the ESR and C and leakage time constants in the design to determine what range of parallel cap types are required. Each dielectric type has effective time constants which may be bias sensitive in high k ceramics , so they must be shunted with insensitive plastic types. By this I mean the series charge C*ESR=T and C*Rleak and compare these to your spectral currents, which for a simple buck include at least 5 harmonics of the pulse rate.

I believe your test methods are inaccurate because C is defined by a low current sine over a DC bias and you are not testing this way as all good LRC meters do for standarization. . For example low ESR e-caps range from 1-10 us and are much higher C density than platic, but for high frequency, plastic caps have lower ESR and are non-inductive but smaller C so since impedance at say 100kHz is crucial, you need a holdup at 2 Hz and a low loss at 100kHz, which can be derived by these Time constants, or alternatively converted from 60Hz dissipation factors.

REVIEW the choices https://product.tdk.com/info/en/products/capacitor/ceramic/mlcc/productguide/index.html
REVIEW my comments.
Provide links to your cap choices and later list ALL your design requirements in order if MUST Have and NICE TO HAVE.. for MTBF, space, spectral current, Zc(f). Then derating factors for aging and environmental stress factors including bias.
There may be a solution with a parallel plastic cap (which is the closest to an ideal cap) or not, depending on above.

There are certainly other ways to examine this, like ripple spectrum current and RMS current, or ESR ratios of source impedance to storage ESR to Switch RdsOn to load I(f) where Z(f)*I(f)= V(f) ripple, but I prefer this way, for now.
 
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H Tony, most of that... whoosh!

I have however found the problem, despite my multimeter indicating 47-52uF (which may or not be correct, but two suppliers in China indicate they read 75-80uF) it is actually heat that is destroying them. I was soldering on wires using a low heat on my solder station and it kills them. Any heat kills them in fact.
 
perhaps the request to provide link to datasheet didnt go over your head and the need for plastic in parallel.. sorry but this is basically Ohm's law applied using ESR and Z(f) as a function of f.

Datasheets will have a thermal profile. For SMT, it is often 3 sec max at liquidus phase of solder using 5 seconds max for solder iron contact time, pref. 3 sec. If you took longer, then you need to hone your solder methods.

They wont tell you this hand soldering method, because SMD caps need a preheat and smooth thermal profile. Hand soldering SMD caps should not take more than 3-5 seconds,
 
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Well I have a real problem here. To be stable it needs 15 of these so called 100uF ceramics (although they do seem easily damaged by heat and I can only try my best there).

Or 1 x 330uF electrolytic, which wont fit in the case. Looking at Tanalium SMD's...

ESR limitation? The ceramics are X7R. The MP2307 recommends X7R on the input to control ripple. Can't find anything in the datasheet on ESR other than it states it as being low. https://www.farnell.com/datasheets/1913358.pdf
 
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About to order some Tantalum's, 220uf x 2 - it's the only thing that'll fit, however the self-healing feature of solid tantalum requires oxygen, does that come from the air I intended to shut off by putting filler? :)
 

Mine aren't getting hot though, not until the soldering iron touches them,, then they display that effect ... permanently.

I would also expect the ratings to be DC, so 0-21 VAC doesn't work with 25 VDC rated caps. Also see: **broken link removed**

Sorry I'll explain that bit better, AC is peak clipped by zeners at 20 or 21v and rectified. In the bench setup I'm using about 7.4v AC / 50Hz.
 
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Here's a picture to show where I'm at.

If I remove all of the capacitors (excluding the one 100uf already on the pcb) and add a 330uF electrolytic it's stable at a 1A (5v/5ohm) current draw from the buck, where stable is minimum voltage drop from the output.

Or I have to add 26 of the 100uf 25v capacitors before it stable (thought it was 15, I was wrong).

It shouldn't be ESR with X7R, there's no heat and the soldering iron is used only briskly, I can't believe I've damaged them all - you can even see how crap the soldering is as I try to keep it on as little as possible.
 

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1. Originally, I asked for a list of your design specs in order of priority, but not getting very far.
These are useful to define and verify your design, so get. started.

2. I said hone your solder methods, you have gobs of cold solder joints. clean copper pads, tin the pads then tack on one end, solder finish the other after cold, the finish the tacked on joint. You are shorting out the top end layers out of 50-100 layers. That reduces C by poor solder temp control!!!

MTBF= ? @ xx 'C
V in min max
Efficiency
Load type, linear, reactive ? moving magnetic load, eg solenoid or motor
Vout I out peak
Step load, rise time
Voltage Tolerance
, ripple, Vpp
load regulatuon
input regulation
Power source impedance or what step load causes a 30% drop in input v.
max temp rise of hotspot? max ambient range?
Convection or conduction heat flow design? Rja=? worst case desired , consider 80'C max at max load and ambient


3. Next ESR and SRF analysis of every passive part from source thru convertor to load and calculation of zeros and poles (Laplacian not binary) thas Effective series Resistance and Series Resonant freqeuency for C and parallel self-resonant f, for L.

These MUST be much greater than switching freq, fSW

e.g. switching rate = fSW =340 kHz so SRF> 1.3MHz, this is negotiable to lower values if you use edge mount on PCB and/or use 50V caps

c3216x7r1e107k fs= below above fSW, no good,,also non-stock

50V better than 25V because any X7R MAY drop up to 90% C near rated voltage !!! such as 20V. So read da specs.

Factor C vs Vdc in derating, determine SRF and make it >2 fSW your switch rate higher the better
examine specs of ESR, SFR and $ for various 50V ceramic caps
https://product.tdk.com/info/en/documents/chara_sheet/C3216X5R1V226M160AC.pdf. READ and UNDERSTAND or ASK ok?

https://www.digikey.ca/product-detail/en/tdk-corporation/C3216X5R1V226M160AC/445-8045-1-ND/2792165

When I meant parallel caps, I was suggesting a low ESR plastic like 0.1uF with 10uF ceramic may work. but cost ESR and SRF with V & C value, size , temp, tolerance etc ALL affect cost
 
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thats 22uF 50V is better due to SRF and ESR. , you look up values and report back others.

When in doubt copy their reference design.

**broken link removed**
 
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Hi Tony,

Lots to go on. No offence intended, at this point I don't want to go through the entire circuit, the rest doesn't have a problem - it's only the smoothing/input cap.

340khz is correct, I know nothing about Series Resonant frequency but I'll look it up now and try to understand what it is. I take it that's what "Z" means on the C3216X5R1V226M160AC.pdf datasheet and for 340khz it's about 0.06 "Z", but that's not >2 fSW, so I'm wrong?

Worth mentioning nominal voltage in is 6V AC (dynamo). Voltage rises under no load so when pulling current (which is when the input capacitor displays the problem input voltage will be 6v AC/8.41V DC). I'm using a 10V AC transformer as my 6V 30VA transformer order still hasn't arrived. I would still have thought it would work reasonable the same though it's not that close to the 25V cap limit. Clearly I'm making too many assumptions already however!
 
if you don't analyze the problems with ESR from end to end, then it will reoccur with aging.
Z(340kHz) appears to be 60 mOhms as you say due to 22uF with 0 Vdc bias.
SRF is ~1MHz and ESR is ~20mOhms . The RdsOn switch inside the regulator is 100 mOhm so the cap losses will be smaller. ..good.

load >> 1 Ohm. linear.. ok
Are you planning to drive LEDs? what kind?
 
if you don't analyze the problems with ESR from end to end, then it will reoccur with aging.
Z(340kHz) appears to be 60 mOhms as you say due to 22uF with 0 Vdc bias.
SRF is ~1MHz and ESR is ~20mOhms . The RdsOn switch inside the regulator is 100 mOhm so the cap losses will be smaller. ..good.

load >> 1 Ohm. linear.. ok
Are you planning to drive LEDs? what kind?

It just occurred to me from you last input on the dynamo that your lowest f and C value mus be able to hold a charge for at least 5 to 10 cycles within 10% at max load.
so. what is its max load capability or Vdc, Vac for test condition at input and f minmum. and C value.
 
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I couldn't find any data for the 100uF cap though, or any for that series, where does it say 'Z' is high @ 340KHz?

Current test condition - 10V AC 50Hz (SIN) / 14V DC.
Real world condition - 6V AC (0-300+Hz says multimeter) but chip on PCB monitors frequency and shuts Buck off at around 25Hz.

Current test loads are resistive, 5, 10 and 50 ohm. Output no load is 5v.

At 50 ohm and single capacitor output voltage doesn't drop, or minimal. Drops to 2.6v @ 10ohm (extra 100uF electrolytic will resolve drop to 4.88v - ok) and drops to 0.8v @ 5ohm (extra 330uF electrolytic will resolve drop to 4.75v - ok).

5ohm = 1A, max real-life current draw.

Under dynamo conditions the voltage drop isn't an issue as at low Hz USB devices that are high powered will have detected voltage drop and switched to a lower power draw, while at faster speed the problem with the capacitors having insufficient charge is mitigated by the higher AC frequency. I'm therefore being a little pedantic in making it work well at high load / low frequency as this is actually an impossibility in real life, but adding capacitance allows me to reduce the cut off point (I think it was 40Hz before, now it's 25Hz).

My focus is why the ceramics can't replace the electrolytic. I'm still a bit confused by the terms, ESR I get and being X7R it's low not to be a factor. SRF ... is resistance but varies per frequency, or rather its like the capacitor in a tweeter high-pass allowing the signal to pass unfiltered, so the SRF must be higher that the change in voltage caused by the buck's switching demand or it effectively shorts? Is my understanding correct?

I hope the figures help but bare with me if not. What else, the MP chip is using the standard reference design with a 15mH inductor. The output is very clean and efficiency is quite incredible really so not a problem here.

Andrew
 
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