Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.
Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.
Dear Mike,
I have gone through this app note already.The problem is that my DAC has some gain errors, I don't know how to nullify this error.
this note suggests that INL can be measured after the other errors are nullified
if you have some example workout, it would have been a lot help...
Hi teachers out there,
I have designed a 4-Bit DAC whose Output is as shown in the attached simulated.txt.
I need to calculate the INL and DNL of the DAC. It also has some gain error.
I tried calculating the dNL and INL. But I think something Fishy is going on with my calculations.
Please...
Dear all,
ok Now I have some grasp on CMFB Design, the AC response looks good (may be). But my opamp doesnot work during transient simulation. Can you guys help me with that.
I have uploaded the schematics, model file, and png files for output of AC and transient responses.
please help.
gopal
Dear all,
I have designed a two stage opamp. I cannot do its CMFB Circuit. What is the procedure of designing a cmfb circuit for a two stage opamp.
can anybody give a full design example of an opamp with its CMFB and bias circuit. Help appreciated.
my design of two stage opamp is
(μnCox≈246.74...
Hello everyone,
I have been facing problem in designing a folded cascode CMOS opamp. I have designed the mosfets aspect ratios for the amplifier circuit but i could not design the bias circuit. I admit i am not very good at designing circuits. so can people here help me with the bias circuits...
Dear all,
I have designed a CMOS LDO with specifications
ILoad=50mA
Vdropout=200mV
the design was simulated using LTSpice IV
I just did the transient analysis and found the output voltage is good as expected.
My problem is,
I dont know how to simulate the PSRR values, the Slew rate, and what...
You edited the schmatics i uploaded? And what u did was "connected a vss instead of gnd, and connected one of the inputs to gnd?
That means design is correct is it?
If thats it... Can u help me to find out the psrr, cmrr, slew rate, and other specs of opamp using ltspice simulation.... ...
I dont understand what you mean... I have attached a model file .. design specification and it is a simple two stage opamp. it can be found in the internet and as is designed in my post..
Dear all,
I am trying to design a two stage opamp. I have gone through texts to equip with basic ideas to design a opamp. The problem is dont know how to choose the ICMR Values and the values of Vth1max, Vth1 min, Vth3max. The Design Procedure i used is as follows.
(μnCox≈246.74 and...
Thank You eTech. your switch model works as needed. Further more, I need to know the internal circuitry for the switch. I am afraid but Can you please send me the internal diagram for switch. I think you designed the switch using the SW from LTSPICE. Or did you do something else. I am poor at...
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