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help in design of CMFB Circuit for two stage fully differential opamp

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Gopal Adhikari

New Member
Dear all,

I have designed a two stage opamp. I cannot do its CMFB Circuit. What is the procedure of designing a cmfb circuit for a two stage opamp.
can anybody give a full design example of an opamp with its CMFB and bias circuit. Help appreciated.
my design of two stage opamp is

(μnCox≈246.74 and μpcox≈92.75

Power Supply : ±1.8V
ICMR= ± 1.6V
| at Vin = - 1.6 , Vth1min = 0.31 Vth3min = 0.432 |
| at Vin = + 1.6 , Vth1max = 0.622 Vth3max = 0.433 |
| These values are found using the simulation of the |
| diff amp in the Circuit shown in the opamp.asy file |
| I hope the values are correct. |

1. Cc=0.22*CLoad=2.2pF ≈3pf(adjusted)

2. I5=SR*Cc= 10*3= 30μ

3. gm1=GBW*Cc*2π=94.24μ
(W/L)1= gm1^2/(μnCox*I5)= 94.25^2/(246.79*30)=1.2
4. (W/L)3 = I5/(μpCox[VDD-ICMRmax-Vth3max+Vt1min]^2)
=30/(92.75[1.8-1.6-0.433+0.31]^2) =54.55 ≈ 54
5. VDSSAT5 = ICMRmin-VSS-√(I5/β1)-Vth1max
= -1.6+1.8-0.3182-0.622 = -0.103722
(W/L)5 = (2*I5/(μnCox*VDSsat5^2)) = 22.91 ≈ 23
6. gm6 = 10*gm1 =942.4μ
gm4 = √(2*I4*μpCox*(W/L)4) = 387.62μ
(W/L)6 = (gm6*(W/L)4)/gm4 = 131.28 ≈131
7. I6 = ((W/L)6*I4)/(W/L)4 = 36.38 ≈36
(W/L)7 = (I7*(W/L)5)/ I5 = 27.89 ≈ 28

For CMFB I searched but cannot find a detail design methodology. Please help me design a CMFB


Gopal Adhikari

New Member
Dear all,

ok Now I have some grasp on CMFB Design, the AC response looks good (may be). But my opamp doesnot work during transient simulation. Can you guys help me with that.
I have uploaded the schematics, model file, and png files for output of AC and transient responses.

please help.
gopal AC Response Fullly diff opamp.png transient sim.png



Active Member
work during transient simulation
you spec ±1.8V and you optimistically supply it with ±900mV
you don't step the voltage source at startup = your amp may take up to 10-s of seconds to initialize itself to normal operational state (especially when using ideal power sources and perfect biasing (a reverse diode or 2 in series to rail from any of the outputs may cancel the least))

also if there's not enough power to drive the output (an output stage design malady) then your AC may pass but the transient is externally set by biasing resistors effect on outputs -- don't put anything at outputs differ/alternate slightly the inputs by ±(5...2000)µV to see if the outputs swing at all
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