Correct. Without that "dead spot", the circuit cannot function.To start with, the two 13v zeners will have a "dead spot" of 2v because they add up to 26v for the 24v supply.
It is more like 1.2 V (0.6 V Vcesat each).On top of this the base-emitter junctions at the top and bottom will add another 1v.
Nope. First, the input is 5 Vpp; it says so right on the drawing. The input must be greater than the dead band to prevent cross-conduction in the output stage.This means the input voltage will not have any effect when it is rising and falling by 3v because this is the "gap" between turning on the bottom zener then the voltage falling and turning on the top zener.
That is true for the circuits in posts #11 and #12, but this circuit is not a linear output stage so none of that applies.Normally "biasing diodes" are just at the point of turning ON, so the rising or falling signal will pass through the diode, even when it is a few millivolts.
Correct. The circuit is designed for a 5 Vpp input signal. It says so right on the drawing.Any voltage below 3v will not be transferred
The 1K resistor is there to limit the base current in the output stage transistors. As you can see from the schematic, they are saturated switches, not linear amplifiers. Once the resistor is selected, the capacitor is calculated based on the minimum frequency or maximum 1/2 cycle pulse width of the input signal.a 5v signal will have some attenuation in the 1k as well as the 2u2.
In post #1 the TS says the signal source is a function generator, not a logic chip, and in post #3 he says he can adjust the output as needed. He mentions +/-5Vpp as an example, so once again your analysis does not apply to this thread.Most 5v signals from a digital source are less than 5v as the output of most chips is 4.5v max and 0.5v min. This gives a 4v p-p signal and the other two losses makes this circuit very unreliable.
What you still do not get is that this is not a linear amplifier circuit. It is not a non-inverting complimentary emitter follower. It is two complimentary inverting saturated switches. The biasing diodes are selected to guarantee that they *never* are both at the point of turning on at the same time; that would be a disaster for the output transistors.
When the input is 0 V, C1 charges up through Q1, D1, and R1, until it has approx. 10.4 V across it (24 V - 13 V - 0.6 V). When the input changes state and starts to move toward 5 V, the other end of C1 moves up. This almost immediately turns off D1 and Q1. As the input continues to rise toward 5 V it crosses 3.2 V, making the other end of the capacitor 13.6 V, and D2 and Q2 start to turn on. By the time the input is at 5 V, Q2 is fully saturated. Now the voltage across C1 is only 8.6 V. The input changes back to 0 V, pulling the capacitor down to 3.6 V, and it starts charging up through D1 and Q1 again.
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