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Simple Question regarding divide by 3 counter-Please help!

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fouadalnoor

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Hello guys,

I am trying to fully understand how to design a divide by 3 counter myself.

I do understand most of the theory behind why its "divide by n" but I find it a little confusing sometimes.

To design a divide by 3 counter I did the following (correct me if i'm wrong)

1. I Drew an ASM Chart with 3 states. I am using two outputs on my D-type Edge triggered (positive) bistable.

2. I made a truth table (with present/next state) and then got my equations for the inputs (Da and Db)

I got the following Equations:

Da = Qa(Bar)Qb + QaQb(bar)
Db = Qa(bar)Qb(bar)+QaQb(bar)

3. I drew up the circuit and got it looking as shown in the attached picture.

- It Does work and counts up to three as in 00, 01, 10,11,00... etc

The thing I am a little confused about is that in a divide by 3 it's supposed to be High 1/3 of the time right? Would my design be wrong as it's only off when its 00? If my design is correct please explain exactly how its "divide by 3" (Does it simply mean dividing the input frequency by 3 which means it will only count up to 3?)

Thanks for your help!

Fouad.

Thanks!
 

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- It Does work and counts up to three as in 00, 01, 10,11,00... etc

The thing I am a little confused about is that in a divide by 3 it's supposed to be High 1/3 of the time right? Would my design be wrong as it's only off when its 00? If my design is correct please explain exactly how its "divide by 3" (Does it simply mean dividing the input frequency by 3 which means it will only count up to 3?)

That's not dividing by 3. It's dividing by 4.

I don't think that you need as many gates as that to divide by 3. You'll need two flip flops but far fewer gates.
 
Is it required that the counter states be 0,1,2,0,1,0,... or is the requirement that it divide by three, without regard to the actual state progression?
 
Well, I'm pretty much confused now as to what is meant when you get a divide by 3 counter (im studying for my exam hence im trying to learn it)


Basically I just want to use D-Type bistable's to get an output that is 1/3 of the clock. (whatever way that might be)

And can someone tell me why my output is divide by 4?

Surely divide by 4 would go: 000, 001,010,011,100 and start again?
 
fouadalnoor,

Code:
And can someone tell me why my output is divide by 4?

The short answer is that it has 4 different states.

Ratch
 
fouadalnoor;939489 Surely divide by 4 would go: 000 said:
No, that would be a divide-by-five, as there are five states. The five states are 0 (counts as the first state), 1, 2, 3, and 4.
 
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Ah!!!! So THATS how it works...

00,01,10.. IS A DIVIDE BY 3...

00,01,10,11 ..IS A DIVIDE BY 4..

and so on!?

Hmm, ok I shall design another one for Divide by 3 and we shall see (so the divide by N simply means number of states?) Thanks!.

I guess I could have simplified it using only 1 NAND gate like Diver300 has but anywho, is it ok?
 

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This one counts 0,1,3,0,1,3,... Any of the four Q, Qbar outputs divide the frequency of the clock by 3.
 

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Hmm, ok I shall design another one for Divide by 3 and we shall see (so the divide by N simply means number of states?) Thanks!.
Yes, that is what it means.

It's like there being 60 seconds in a minute. A clock divides by 60 by having 60 different states, but they are numbered 00, 01 .... 58, 59

I guess I could have simplified it using only 1 NAND gate like Diver300 has but anywho, is it ok?

My circuit uses an AND gate, and I don't think it will work with a NAND gate.

Your circuit will work, but the top left AND gate isn't needed. The black output line from that gate will always be the same as the black input line, so you might as well remove the gate and just join the two black lines together.

At which point it becomes exactly the same as mine, and very similar to MikeMI's circuit.

The reason that your circuit can be simplified is that when you are designing a circuit to count 00, 01, 10, 00, 01 etc, you do not need to worry about what happens if it gets to 11, because that will never happen.

It's probably a good idea to make sure that if the circuit happens to turn on with both flip-flops set to 1, then it doesn't lock up or count in a different way forever.

If the counter were to get to 11, the extra gate that you put in would make your counter go to 00 next clock cycle. My design would go to 10 next clock cycle. Both designs then count as normal from then on. So unless it is a design requirement to go from 11 to 00 in one clock cycle, that gate isn't needed.
 
Hello,


The simplest way to build a divide by N counter is to first build a binary count circuit (FF's) that can count up to at least N and then build a detector circuit that can detect a count of N and have the output of that detector circuit reset all the FF's to zero.
For example, for a divide by 6 circuit we would need at least 3 Flip Flops and a little circuit that can detect a binary 6 (because N=6). The detect circuit is then used to reset all the FF's to zero. For this example, the count would go 0,1,2,3,4,5, and as soon as the count becomes 6 the detect circuit resets all the FF's back to zero so the count again goes 0,1,2,3,4,5. So it will keep repeating, 0,1,2,3,4,5, 0,1,2,3,4,5, 0,1,2,3,4,5, etc., which is a divide by six counter.
The detect circuit is often nothing more than a NAND gate with enough inputs to detect the full bit width of the counter plus some inverters. For the example above, we would be using 3 bits thus we would need at least a 3 bit NAND gate. A binary 6 with three bits is 110 so we need to invert the zero bit and run that into one NAND gate input and run the other two right into the NAND gate. Thus, the NAND gate outputs a 1 until such time as the count becomes equal to 6 and then the NAND outputs a 0 which resets all of the FF's (many FF's have an inverted true reset input ie 'Not Reset').
There is a trick we can use however, because the above detect circuit assumes a totally random count but the count from a binary counter is not random but is in sequence 0,1,2,3,..., etc. This means that some states can only appear after some other states and that means some other states will never appear. This means we can simplify the detect circuit. If we assume that the counter starts at zero the count goes 0,1,2,3,4,5, and so far all that time the 1st and 2nd bits never both equaled 1 at the same time, but at a count of 6 suddenly they both do, so we can simplify the detect circuit knowing this and get away with using only a single two input NAND gate with the inputs connected to bits 1 and 2 (not to bits 0 and 1). In this way, when a count of 110 occurs the NAND output goes to 0 and resets all the FF's but never any other time will this occur.
Thus, with a 3 bit counter and a single two input NAND gate we have constructed a divide by 6 counter.
Other counters are constructed in a similar way sometimes needing a NAND gate with many more inputs, but it never hurts to look for short cuts either.
 
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Another trick is to start with a "Johnson" counter, which is a form of shift register ring counter where the Q-bar of the last bit is fed back to D input of the first bit. A Johnson counter is an example of a counter that counts in a Gray Code

A two-bit (four-state) Johnson counter does not count in straight binary sequence, rather it counts 0,2,3,1,0,2,3,1. No gates are used at all. To shorten the sequence by one count requires just one two-input gate. That is the circuit I posted above...
 
Guys, I have this question from my past exam paper:

"A video surveillance system is provided with a (binary) clock signal oscillating at 10Hz. This provides too much data for the surveillance system to store as it has capacity for only 1/10 the amount of information. Design a circuit which accepts as input the 10 Hz signal and provides as output a signal which is a binary signal oscillating at 1 Hz. Use only positive edge-triggered D-type bistables"

When I tried to do it I realised I must divide the input frequency (clk) by 10. Thus I need a divide by 10 bistable... but when I tried to make one I needed to have 4 outputs (QaQbQcQD) counting from 0-9 which means I need 12 AND gates with 4 Or gates connected up to each Data input of the respective bistables. I also had to draw an ASM chart and then get equations for Da,Db,Dc and Dd to know how to wire up all the AND and Or gates...

But isnt this all a little too much for an exam paper (its supposed to take me about 40 mins..)

am I doing something wrong?

(I know that I could create a simple divide by 8 counter by simply having 3 D-types connected together where the Q(bar) output goes back into the input (D) of each bistable and then connect up each output Q into the clk of the next output...)

Another question which I didn't know how to approach was

"Design a circuit which multiplies a 3-bit binary B2B1B0 number by 4." (The number after The B's is in subscript)

Thaaannkkks for any help!
 
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Here is a divide by ten counter built out of D-flops that would take about 2min to draw on an exam paper.

Multiplying any binary number by 4 is as simple as left-shifting two bits to the left, and padding it with two zeros on the right end. Proof left to student.
 

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Ah Thats pretty cool! The thing is, I haven't learnt how to do it using a Johnson Counter, normally I would just use the ASM chart with 10 states to do it. I thought the ASM will give me the simplest answer?
 
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Ah Thats pretty cool! The thing is, I haven't learnt how to do it using a Johnson Counter, normally I would just use the ASM chart with 10 states to do it. I thought the ASM will give me the simplest answer?

Not necessarily,

Back in the days when flip-flops were expensive, and gates where cheaper, there was a push to minimize the number of flops, even though it meant more gates. The Johnson counter adds an extra flip-flop, which means that there are potentially 2^5=32 total states, but we only need 10 out of the 32, so we trade the extra flop for fewer gates.

Another advantage of the Johnson counter is that it is a synchronous counter which counts in Gray code, meaning only a single bit changes on each clock edge, which allows for glitchless decoding of the outputs (unlike a conventional binary counter).

Johnson counters have one little dark secret; look up "Hazard" in this context. Another exercise for the student...
 
Thanks for the reply,

I have now taken a better look at Gray code and I can see that it will simplify the circuit. But in your circuit you didn't use any gates at all while if I were to construct a divide by 8 counter using gray code I will still need AND and OR gates wouldn't I?
 
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Nope, a divide by 8 would be four D-flops with Qbar of the last to Din of the first.
 
Gosh... Ok, well thats settles it! I need to read more on how to make divide by N counters. Any links you can give that will explain how to make them using only D Type FF?

Thanks.

Fouad.
 
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