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output error voltage and drop-out voltage in LDO

Discussion in 'Mathematics and Physics' started by anhnha, Mar 24, 2014.

  1. Jony130

    Jony130 Active Member

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    In this type of a voltage regulator error amplifier and PMOS are supply from the same voltage. But even if error amp is supply from the large voltage than PMOS. The error amp will still be able to turn ON PMOS.
    Initially when Vout = 0V and Vfb = 0V the error amp see large different between Vbg and Vfb (Vdiff = 0V - 1V = -1V).
    The error amplifier will now amplify this negative Vdiff voltage to produce a negative-going output voltage.
    And this is why the output of the error amp will go toward negative direction ( towards 0V). And this voltage for sure will turn ON the PMOS.
     
    Last edited: Mar 30, 2014
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  2. anhnha

    anhnha Member

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    Thanks, Jony.
    That seems to be a good explanation. I mistakenly calculate Vdiff.
     
  3. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi,

    You have to look at this one block at a time. Look at the op amp only. For any given output, if Vbg goes high the output goes lower. That's because it is an inverting amp. I assumed that when i say A1 you realize that it is negative. But since A2 is also negative when we combine the gains we get a positive value because we multiply two negatives.

    So with zero Vfb when Vbg goes positive, the output of the op amp goes lower.

    Now look at the PMOS. What happens when the input goes lower? The device turns on harder, and so the output voltage Vout goes higher.

    Now look at Vfb going to the op amp. What happens when Vout goes higher? The Vfb goes higher. Vfb going higher means it gets closer and closer to Vbg and so the difference gets smaller.

    Now look at the op amp output again. As the difference gets smaller the output gets higher.

    Now look at the PMOS again. As the input gets higher the device conducts less. As it conducts less the output Vout goes lower.

    It is this basic loop action that causes the output to get regulated at the set point set up by the reference voltage Vbg.

    If this still isnt clear perhaps we should look at a complete numerical example.
     
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  4. dave

    Dave New Member

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  5. anhnha

    anhnha Member

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    Thank you. I got it now.
    I made a mistake about the sign of Vdiff and that caused confusion.
     
  6. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi,

    Oh ok no problem :)
     
  7. anhnha

    anhnha Member

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    Could you talk about this?
     
  8. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi,

    Yes, but i think i will be able to talk more about it tomorrow.

    For now though, what we would do is include at least one capacitance say at the output. From there we would see the gain A2 change because now the voltage output (generated by the PMOS as before with only resistance on the output) is dependent on the time response of the output network. Before it was just a resistor so the time response was instantaneous. But as capacitance is added this changes and we see the gain having a phase shift and all that stuff. This puts constraints on the gain where the gain may be limited to some max and/or min value in order to prevent oscillation or the possibility of oscillation.

    The only difference really is you have to write the equation for the response using some capacitance with some ESR value also. The equation for the output load then becomes equal to the parallel combination of the R1+R2 and the impedance of the ESR and capacitor.
    The ESR and capacitor come out to R+1/(s*C), and that in parallel with R1 and R2 where R1 and R2 are large means we effectively see just R+1/(s*C) at the output, and that converts the PMOS current into the voltage we needed for Vfb. The gain A2 (negative) then becomes gm*(R+1/(s*C)) instead of just gm*R as before, and R here is the ESR now not R1+R2.

    Because this is such a simple circuit we can then look at the time response or do a full root locus allowing the gain gm and A1 to vary as a lumped quantity gm*A1.

    You could probably do this yourself if you want to since you were able to do the equations in the article. See what you think about this.
     
  9. Jony130

    Jony130 Active Member

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  10. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi again,

    Thanks Jony for the links.

    Also, i made a simple mistake in the equations before. I'll correct the basic expression here now.

    The first expression is:
    Vdiff=Vfb-Vin (Vin is Vbg)

    That gets multiplied by the gain A1 which itself is positive:
    Va=Vdiff*A1=(Vfb-Vin)*A1

    Next that gets multiplied by the gm, and gm is negative here because the PMOS is an inverer:
    Iout=Va*(-gm)=(Vfb-Vin)*A1*(-gm)=(Vin-Vfb)*A1*gm

    Then we have Vout from Iout (with resistive load only):
    Vout=Iout*RL=(Vin-Vfb)*A1*gm*RL

    and since Vfb=Vout we end up with:
    Vout=(Vin-Vout)*A1*gm*RL

    and solving explicitly for Vout we get:
    Vout=(Vin*gm*A1*RL)/(gm*A1*RL+1)

    so with gm=0.1, RL=10,A1=100,Vin=1 volt we get:
    Vout=100/101 volts.

    so it is slightly less than the reference, and increasing the gain reduces the error (gets Vout closer and closer to 1.000).

    Once we get the capacitors in the circuit we have to multiply A1 by GRC and Iout by Zo so we get:
    Vout=Vin*gm*Zo*A1*GRC/(gm*Zo*A1*GRC+1)

    where Zo is the output impedance and GRC is the gain of an RC network between A1 and the ideal PMOS gate which allows for the PMOS input capacitance, so GRC=(1/sC)/(R+1/sC).
     
    Last edited: Apr 1, 2014
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  11. anhnha

    anhnha Member

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    Thank you.
    I think I need to go back a little. As you said, increasing the gain of the error amplifier and PMOS, the output error voltage is reduced.
    Please see the picture on the left of post #3.
    Here is the result of the calculation above.
    Vout=(Vin*gm*A1*RL)/(gm*A1*RL+1)
    As A1*RL goes to infinity, Vout approaches (Vin*RL)/gm.
    For this computation, we just mentioned about the output error voltage caused by limited voltage of amplifier and PMOS, right?
    That is because we consider the voltage at the source of PMOS is constant.
    However, it is not the case. The power supply at source of PMOS is not a constant at all. It will cause more ripple at the output in addition to the one caused by limited gain of PMOS and error amplifier.
    Is that correct?
     
  12. anhnha

    anhnha Member

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    Could you help me with this problem?

    [​IMG]
     

    Attached Files:

  13. Jony130

    Jony130 Active Member

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  14. anhnha

    anhnha Member

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    Thanks, Jony.
    I am still confused. In post #29, we see that the output error voltage is reduced as the total gain of error amplifier and PMOS increases. However, we didn't take the noise (ripple of the power supply) into account.
    I think we considered the case the power supply is perfectly constant. In that case Vout is only good as the total gain of error amplifier and PMOS increases.
    My opinion is that maybe we need to model the noise from power supply in calculating output error voltage.
     
  15. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hello,

    For that Vout as A1*RL goes to infinity Vout becomes equal to Vin.

    I think you really have to go over this a little more before you start considering what the power supply is doing. Also, when you do start to talk about things like this you have to be very specific about what it is you want to know. For example, most true noise has a mean of zero, so the average effect on the output is zero. If you want to figure out how much of the AC part gets to the output then you have to do an analysis of the circuit as if the power supply was another input.
     
  16. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi,

    It's not very clear what it is you want to do here or why you want to do it..
     
  17. Jony130

    Jony130 Active Member

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    We don't need to model the ripple voltage from the power supply in this circuit. Why ? Because from the feedback theory we know that any external disturbance will be reduces by a factor of 1/(1+Aol*B) ; Where Aol is a open loop voltage gain. And B is a feedback factor (feedback gain) in our example
    B = Vfb/Vout = R2/(R1 +R2). In the example show in post 29 by MrAi we have
    gm=0.1, RL=10,A1=100,Vin=1 volt and B = 1,

    Aol = 100 * 0.1*10 = 100V/V , therefore the ripple voltage at source will be reduce 1/101 times, this means that 1V change in PMOS source voltage will causes 0.0099V change in output voltage.

    I'm not so sure about that (I may be wrong), but I think that this model can be use to confirm this result.

    121.PNG

    So we have dVou/dVsup = line regulation = gm*RL/(1 + A1 gm RL)
     
  18. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi,

    I get a similar result after including a little gate capacitance and A1 amp output resistance. I wanted to include gate capacitance because that looks like a low pass filter for the noise from the supply voltage Vcc for the gate of the PMOS.

    I get the frequency response as:
    VoutAC=(gm*E1*R2)/sqrt((gm*A1*R2+1)^2+w^2*C1^2*R1^2)

    where
    VoutAC is the AC output amplitude in volts peak,
    R2 is the load resistor in ohms(no capacitive load yet),
    R1 is the A1 amplifier output resistance in ohms,
    C1 is the equivalent gate capacitance from the gate to the source in farads,
    E1 is the AC supply voltage noise peak in volts peak,
    gm is the transconductance of the PMOS again,
    w is the angular frequency of the noise (and w=2*pi*f where f is frequency in Hertz).

    Noting that an approximation of this equation leads to the very simple:
    VoutAC=E1/A1

    What this is basically saying is that the output noise generated from the Vcc supply voltage noise (E1) is dependent on the gain of the first op amp A1, and is roughly inversely proportional. So as we increase the gain of the first op amp we decrease the noise as the inverse of the gain.

    This is an interesting result i think. We usually need A1 to be high anyway to get the circuit to work right in the first place.

    What is not included in this view is the fact that the op amp gain also goes down with frequency. So some higher frequencies may not be attenuated. However, a small ceramic capacitor on the output should cancel that effect. We could actually look at this effect too at some point by including a gain decrease for A1 with frequency, probably making it linear like most op amp spec sheets show. Then we would also include a small cap in parallel with R2 (the load resistor to ground in this equation).
     
  19. Jony130

    Jony130 Active Member

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    Thanks MrAl for your analysis. But can you give me more details how can small cap "compensate" op amp gain drop with frequency?
    Or maybe you're talking about output ripple attenuate by this capacitor?
     
  20. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi Jony,

    When i talked about the output cap it was solely to reduce the noise that can get to the output, or appear at the output. Because the gain A1 will drop with frequency that means that the circuit no longer can attenuate noise as well as it could with high gain, so therefore we need another way to reduce noise on the output so i simply reasoned that a small cap should take care of it. So it's not that the cap can actually increase the gain, it just reduces the noise on the output that the op amp normally might be able to do at lower frequencies.
    I'm talking higher frequency noise here too not really power line noise like 50 to 120Hz because those lower frequencies should be able to be attenuated by virtue of the op amp gain.
     
  21. anhnha

    anhnha Member

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    Thank you, Mr Al and Jony.

    Jony, could you send me the LTspice file in post #36? I can't find the voltage controlled current source as yours.
     

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