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Need for these capacitors and resistors

gjoo

Member
Just lead some help identifying the use of a few resistors and capacitors in this circuit. What is the use of c1, c7, c13, c14, c15, c23, c24, c25 and r3,r7, r10?
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C7 (along with C8 and C9) is an imaginary debounce capacitor - but doesn't work - all the other capacitors you list are decoupling capacitors. R3 is the current limiting resistor for the backlight in the LCD display, R10 is a pull-up resistor for SW2, and I can't see an R7?.
 
Where is r7??

If bounce time is << 5 ms the designer has chosen 22ms for Tau suitable for clunky toggle switches or many to reduce finger bounce.

The R4 is to prevent dry contact DC power bounce SCR failure on the MCLR input with enough stored energy to blow and ESD diode so R4 serves as current limiting. The reset time constant is uC specific.

A better choice might be 1 Meg and 10 to 47 nF for R1 C2 to reduce stored energy on intermittent power up and still overpower MCLR leakage (?) worst case.

Although depending on the quality of the switch, it ought to be gold-plated (as all are < 2A) but if not , thought 1uF would burn off any oxide each time it was used. But then if Reset is used a lot, it might burn through the flash plated contacts and then will oxidize and become intermittent many years later. It's an unknown reliability question with a reasoned solution.

The other switch caps are excessively large and 1Meg 10 to 47 nF can be considered and verified.

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C7 (along with C8 and C9) is an imaginary debounce capacitor - but doesn't work - all the other capacitors you list are decoupling capacitors. R3 is the current limiting resistor for the backlight in the LCD display, R10 is a pull-up resistor for SW2, and I can't see an R7?.
Please explain why you think it doesn't work for attack and decay time of Cap charge.
 
According to TI and the chips designed to create POR a 20 ms MCLR or master clear is required.

 
Please explain why you think it doesn't work for attack and decay time of Cap charge.
Try it and see, it's not a satisfactory debounce solution - even if the inputs are schmitt trigger, which they need to be even with a proper debounce circuit. The capacitor will charge and discharge, but that doesn't give debounce.
 
Try it and see, it's not a satisfactory debounce solution - even if the inputs are schmitt trigger, which they need to be even with a proper debounce circuit. The capacitor will charge and discharge, but that doesn't give debounce.
That contradicts theory and practice . I was hoping you could explain your reasoning. The fact is the cap holds the voltage in a microsecond on 1st contact and when open will not change voltage faster than dV/dt = Vcc/RC so if RC=tau is greater than bounce time the logic gate always sees “0” with no bounce to a “1”
 
That contradicts theory and practice . I was hoping you could explain your reasoning. The fact is the cap holds the voltage in a microsecond on 1st contact and when open will not change voltage faster than dV/dt = Vcc/RC so if RC=tau is greater than bounce time the logic gate always sees “0” with no bounce to a “1”

Like I said, try it and see - and compare all the many texts about debouncing. It's also absolutely crucial to use a schmitt input, or even a proper debouncing circuit won't work.

With just the resistor and capacitor the capacitor charges slowly, but discharges rapidly (effectively instantly), you need it to discharge slowly as well - and the afore mentioned schmitt input as well.
 
Your experience is easily explained by noise or a shift in voltage on supply and ground as the input passed thru the transition voltage when the IC draws about 0.5 mA more current. If the ground level rises as the input rises the input state can oscillate and remain at Vcc/2 or ring for some # of cycles faster than the bounce interval. This is partly a PDN design issue.

So I agree if one has high enough parasitic inductance or resistance on Vcc or ground then Schmitt Triggers are necessary. But with this understanding it can be avoided. The 3.6V and 5.5V logic is higher speed and draw current during transition thus a solid supply and ground with decoupling will be more sensitive to this problem this failure mode. But again the rise in current only at the transition midpoint is about 0.5 mA. When doing this, software debouncing is normally otherwise state changes or interrupts may be masked.

If the pushbuttton triggers a counter , again S/W debounce or Schmitt H/W is used but the input will rise to the supply and the state change will be recognized. So we can say it works conditionally. The Unbuffered CD4000 was far more forgiving in this due to much lower transition currents and risetime due to much higher RdsOn internally and on outputs.

This was the kind of explanation I was hoping you would give.
 
Why is higher Rdson better in this situation. I thought it increases transition current rise time , which makes it take longer to turn switch on?

If the pushbuttton triggers a counter , again S/W debounce or Schmitt H/W is used but the input will rise to the supply and the state change will be recognized. So we can say it works conditionally. The Unbuffered CD4000 was far more forgiving in this due to much lower transition currents and risetime due to much higher RdsOn internally and on outputs.
 
A little bit of noise, 100 mV RMS input, 200 mV RMS Vcc, goes a long ways to generating jitter.

Not a complete sim, eg. omitted ground bounce, internal IR drops.....T and V.....

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Regards, Dana.
 
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Hardware debouncing is necessary if the switch feeds logic that will react adversely to multiple edges, such as a counter or a flip-flop.

But generally, there is no need to add hardware debouncing to switches that feed microcontroller pins, since it is very easy to do that in software.

The one reason that I can think of to add capacitors to a switch feeding a microcontroller is if the timing of the code loop is very slow. The capacitor will extend the time of the switch press, making it less likely to miss a fast switch press.
 

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