Logic problem

[georgetwo]

Hello everyone !
I have a problem with drawing a logic cct with 3 input that will give 1 as output when two or all inputs are high (1). Any idear is allowed.

 

[crutschow]

Hint: You could use three AND gates and one OR gate. or four NAND gates.

The rest is up to you. Double points if you come up with both solutions.

 

[MikeMl]

Out = AB + BC + AC

 

[crutschow]

Ok georgetwo. Bonus points. Your turn to do it with all NAND gates.

 

[georgetwo]

Quite easy. I used three nand gates whose outputs are labeled AB, BC, AC. Their outputs are connected to a three input nand gate. The boolean algebra gives AB+BC+AC.
But how did you guys come out with this expression? I need help

 

[MikeMl]

The exact equation that satisfies your original specification of the problem is Out = AB + BC + AC + ABC. Simple Boolean reduction subsumes the last term into the other three. If you like, draw it as a Karaugh Map.

 

[xpi0t0s]

But how did you guys come out with this expression? I need help

From the truth table:

a b c out a.b a.c b.c
0 0 0  0   0   0   0
0 0 1  0   0   0   0
0 1 0  0   0   0   0
0 1 1  1   0   0   1
1 0 0  0   0   0   0
1 0 1  1   0   1   0
1 1 0  1   1   0   0
1 1 1  1   1   1   1

Looking at the "out" column and recognising the embedded AND and OR functions (i.e. 0001 and 0111) you might come up with !a.(b.c) + a.(b+c) as a first guess. You might realise that b.c is true regardless of a and simplify this to b.c + a.(b+c). Then distribute the a to get rid of the brackets -> b.c + a.b + a.c (but only if you have a 3-input OR gate available).

 

[crutschow]

Quite easy. I used three nand gates whose outputs are labeled AB, BC, AC. Their outputs are connected to a three input nand gate. The boolean algebra gives AB+BC+AC.
But how did you guys come out with this expression? I need help

The use of NAND gates for this comes from the observation that for negative logic (0V=logic 1, 5V=logic 0) a NAND gate becomes a NOR gate and a NOR gate becomes a NAND gate.

So first you substitute NAND gates for the three AND gates in the expression. This gives outputs that are 0 only when both logic inputs are 1. You now want to detect when any output from the three NAND gates is low, so you can use a negative logic NOR gate (another NAND gate). Because of the two inversions through the NAND gates you end up with positive logic in and out.

NAND and NOR gates are preferable to AND and OR gates since they don't require an extra internal inversion stage, and are thus slightly faster while using less power.