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Hitachi HM6116ZP-4 CMOS RAM Datasheet

Discussion in 'Datasheets, Manuals or Parts' started by Krumlink, Mar 15, 2008.

  1. blueroomelectronics

    blueroomelectronics Well-Known Member

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    Nice work on the Z80.
    Is the keyboard made of paper?
     
  2. kchriste

    kchriste New Member Forum Supporter

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    Thanks, it was my final year project at BCIT. Yes, the part you see is a piece of tape covered paper. The actual keyboard was one scavenged from an old calculator; the kind with metal popples on a PCB. I drew my custom buttons on a piece of paper with colored pens, covered it with clear tape for durability, and glued it on top of the popple PCB. The display was robbed from the same calculator.
     
  3. Nigel Goodwin

    Nigel Goodwin Super Moderator Most Helpful Member

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    As far as I remember, mine used a NICAD, and the life of those is VERY limited! - I'll try and dig it out and post a picture :D
     
  4. dave

    Dave New Member

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  5. Krumlink

    Krumlink New Member

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    So this is what I think:
    1. Data input into the I/O lines.
    2. Switch Addresses with the Address inputs with Binary, aka address line 1 in 000 0000 0001 and 37 in 000 0010 0101 correct?
    3. All this will be configured with the Write enable and the Read enable stuff, which is easy. I believe I gotz it correct?

    (Then to keep the chip alive I enable CS (Chip select) and GND, or so I think?
     
  6. kchriste

    kchriste New Member Forum Supporter

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    Yes.
    Set your address lines.
    Put the data you want to load on the IO lines.
    Make CS low. ( WR and OE are already high )
    Make WR low and then high again.
    The data is now stored at one address location.

    To read the data back:
    Set your address lines the same as above.
    Make CS low. ( WR and OE are high )
    Make OE low.
    The data is now being outputted on the IO pins.
    Make CS and OE high again and the chip is asleep with the data still valid inside it and the IO pins are disabled.
    Note: The IO pins are typically connected to the data buss of a CPU. They are inputs when WR & CS are low and are outputs when OE & CS are low. They do nothing when CS is high and the RAM is asleep.
     
    Last edited: Mar 19, 2008

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