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Help:Digitally controlled current source

Discussion in 'Electronic Projects Design/Ideas/Reviews' started by abicash, Apr 28, 2009.

  1. abicash

    abicash Member

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    Hi Ron

    I was checking for the monolithic diff.amp. and i found a similar part from Analog devices AMP03
    I think this could be used too?
     
  2. abicash

    abicash Member

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    Hi Ron

    I am proposing this schematic

    1)U3 is the current sink IC
    2)U1 is the diff amp (looking for monolithic ones).Currently will use 7650 with precision 0.1% resistors to correct gain errors.Now the gain of this amp is halved for load resistor above 3ohms using analog switches (U2)
    3)This value (from diff.amp.) is read in an ADC as VDIFF calibration value.
    4)VDIFF is o/p on a DAC (by scaling at appropriately) and inverted (U5) to a VCAL value
    5)VCAL is subtracted from VDIFF and amplified to Gain=100 (U4) and further Gain=100 (it got named as U4 too :eek: )
    6)This value is read on another ADC and 2k samples are taken.

    You have any comments?

    [​IMG]
     
    Last edited: Dec 23, 2009
  3. Roff

    Roff Well-Known Member

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    I see at least two potential problems:
    1. The 4066 analog switch resistances will screw up the gain of the difference amp. I would set up two separate gain networks, with a dual 2-1 analog mux choosing one or the other of them. This will avoid passing current through the switches, so the resistance will be irrelevant.

    2. The output of your Adder amp will be overdriven until VDIFF and VCAL are nearly equal. You will have to protect your ADC from this overdrive, if you haven't already done so.
     
  4. dave

    Dave New Member

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  5. Roff

    Roff Well-Known Member

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    Also, be aware that the common mode gain of the AMP03 (< -80dB) can cause an output offset at VDIFF of (12V/80dB) as much as ±1.2mV. This should be removed by your cal procedure, so long as it is short-term stable (it probably will be). If common mode gain varies between cal and measurement, it will cause errors.
     
    Last edited: Dec 23, 2009
  6. abicash

    abicash Member

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    Hi Ron
    i had thought about the resistance of the switches.But since they will be equal(to an extent),there will be proper resolve of the diff.voltage
    i may be wrong.
    Regarding analog mux..I can use other channels of the ADCs,in that case.
    I think i may have made a mistake in drawing.I havent doubled the Dac voltage for the half voltage measured on the diff.amp.I am really confused :(
     
  7. Roff

    Roff Well-Known Member

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    The equal resistance of the analog switches should keep the common mode rejection high, but they introduce gain errors. Below is how I would implement gain switching.
     

    Attached Files:

  8. abicash

    abicash Member

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    That is neat..:)
    thanks a million..I will try that..
    For the differential amp i have purchased 0.1% tolerance resistors.As i see gain error is very low with that(compared to 1%)
     
  9. Roff

    Roff Well-Known Member

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    Max gain error for unity gain diff amp is 0.2% when using 0.1% resistors. You can figure that out yourself.:)
     
    Last edited: Dec 23, 2009
  10. abicash

    abicash Member

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    A quick question.
    Wont the unused Resistors come in parallel with the ones utilised when the mux switches one way?
    I hope you get what i mean
     
  11. Roff

    Roff Well-Known Member

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    The unused side of the bridge (as drawn, that would be R5-R6) only affects the gain to the extent that it adds a little more current to the load resistor. It does not affect the closed loop gain of the op amp.
    Basically, R5+R6 are in parallel with R7+R8. This parallel combo creates an error current. You have to decide if you can make the resistor values large enough to make this error insignificant.
    As I said, the difference amp is my least favorite method of level shifting the output so that it is ground-referenced.
     
  12. abicash

    abicash Member

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    I have changed the scheme and will be making a board out of this.Please can you comment on what precaution i have to take while getting it done?
    My scheme according to i/p from you...added 3v3 zener at the Vsample
    o/p.I think that would be sufficient.What say?

    [​IMG]
     
    Last edited: Dec 23, 2009
  13. Roff

    Roff Well-Known Member

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    I suppose the zener will work. Keep in mind the zener tolerance, and the fact that the knee on a 3.3V zener is pretty soft. You might not get the use of the full range of your A/D if the reference is 3.3V.
     
  14. abicash

    abicash Member

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    Hi and thanks a lot Ron :)
    i have sent the board for designing.Lets hope everything works out fine.
    Off topic a bit..What does your avatar pic mean?
     
  15. Roff

    Roff Well-Known Member

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    Where are you from?:)
    It means no bulls**t.
     
  16. abicash

    abicash Member

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    :D that brought a smile..
    And i am from India
     
  17. abicash

    abicash Member

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    Hello Ron , First and the foremost ...A very happy new year to you and your family :) .I hope you enjoyed xmas and new years eve :)

    I have got the board and was testing it all these days.Some things are not working as they should :( (as usual)
    Please review it if you have got time :eek:

    [​IMG]

    As you see the set gains are screwed at the o/p of each stage.
    Please comment on ways to improve the design
    Thanks and regards

    EDIT: VCAL is negative value (-85.3mV) .I forgot to add the -ve sign
     
    Last edited: Jan 1, 2010
    • Like Like x 1
  18. Roff

    Roff Well-Known Member

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    On the CD4053, what voltages are you using for VDD (pin 16), VSS (pin 8), and VEE (pin 7)?
    You need to show polarities of measured voltages. VCAL should be negative.
    Looking at U4 as an example, you have something wrong with either the op amp, grounding, or your measurement equipment/technique. Is this built on a PC board? Do you have a ground plane? Can you post a photo of the circuit board?
     
  19. abicash

    abicash Member

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    The VSS and VEE of CD4053 are tied to Ground.The VDD=+12v

    I think i had already done that..please see my text below the schematic.(had forgotten to give the negative sign)

    This is built on a PC board.I haven't brought my Digital camera with me and my phones camera is a meagre 1MP.I will post the Artwork and the layout some time later in the day.
    I measure this with a good calibrated Voltmeter.I don't have a ground plane as such ,but i have connected the grounds from each op-amp individually to the common ground track

    One more thing i noticed:
    I was measuring the voltages at VDIFF & VCAL by providing voltages from a preset to DAC-REF SET and CURRENT SET i/ps.When i connected a MCU to this setup there are severe disturbances :(
    First,the VDIFF at the same currents measures 300-400mV.
    The DAC (12 bit) of the MCU cannot distinguish the smallest voltage scaled on a value 0xFFF=3.3v (or rather,is highly non-linear).I am thinking of creating a table of all the values needed and scale them manually.

    I see a lot of problems here and the delivery date for this is the 10th of Jan.Lets hope all works out fine :)

    Thanks for your time :)

    EDIT: Changed 4053 supplies to VEE=-12v ,VSS=Ground and observed.No change!!!Attached PCB details
     

    Attached Files:

    Last edited: Jan 1, 2010
  20. Roff

    Roff Well-Known Member

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    CD4053 connections were correct before you changed them. CD4053 was connected correctly to supplies, and is not rated for 24V Vcc-Vee.
    Ground routing techniques are critical in millivolt circuits. Even a ground plane may not be adequate. Parasitic ground resistance may have excessive voltage drop due to power supply currents or even signal currents.
     
  21. abicash

    abicash Member

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    Hi Ron
    The 300mv which was there at the o/p of the differential was due to a series current meter(i think) since removing the meter corrected the problem.
    Apart from that the minute errors in voltages are still there.So what would you suggest?A separate ground plane?Did you see my board?
     

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