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Fpga

Discussion in 'Microcontrollers' started by AtomSoft, Jul 23, 2011.

  1. BrownOut

    BrownOut Banned

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    It's prefectly fine. You can also use hex or decimal literals to set the value. Don't fool around with all those 'ones' and 'zeros' if you don't have to.
     
  2. AtomSoft

    AtomSoft Well-Known Member

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    i actually made a program a while ago which converts hex<>dec<>binary... so the bits arent hard to make but hex would be way better or dec
     
  3. AtomSoft

    AtomSoft Well-Known Member

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    ill tell you what; im going to redo this entire blink with speed stuff. from scratch again. But slower :)
     
    Last edited: Aug 9, 2011
  4. dave

    Dave New Member

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  5. BrownOut

    BrownOut Banned

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    There are ways to just use hex or dec directly. For example, use a based nurmic literal:

    16#fff - 4095 decimal
    10#4095 - same as above.

    Or just use decimal iterals implicitly

    Counter <= 4095;

    Counter <= 2e12;

    etc.
     
    Last edited: Aug 9, 2011
  6. AtomSoft

    AtomSoft Well-Known Member

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    Thanks, i have rewrote it all but get warnings

    Code (text):

    ----------------------------------------------------------------------------------
    -- Company:
    -- Engineer:
    --
    -- Create Date:    16:32:16 08/08/2011
    -- Design Name:
    -- Module Name:    BlinkRate - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool versions:
    -- Description:
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity BlinkRate is
    port( Button:   in std_logic;
           Clock:       in std_logic;
           Reset:       in std_logic;
           LED:     out std_logic
    );
    end BlinkRate;

    architecture FSM of BlinkRate is
        signal Count: std_logic_vector(24 downto 0);   
        signal State: std_logic_vector(1 downto 0);
        signal NextState: std_logic_vector(1 downto 0);
    begin

       SYNC_PROC:process(Clock, Reset)
       begin   
            if ( Reset='1') then
                  State <= (others => '0');
                  Count <= (others => '0');
            elsif ( Clock'event and  Clock='1') then
                  Count <=  Count + 1;
                  State <=  NextState;
            end if;
       end process;                        
       
        STATE_PROC:process( State,  Button)
        begin
            case State is
                when "00" =>
                    if( Button = '0') then
                         NextState <= "01";
                    end if;
                when "01" =>
                    if( Button = '0') then
                         NextState <= "10";
                    end if;
                when "10" =>
                    if( Button = '0') then
                         NextState <= "11";
                    end if;
                when "11" =>
                    if( Button = '0') then
                         NextState <= "00";
                    end if;
                when others =>
                   NextState <= "00";
            end case;
        end process;   

    end FSM ;

     
    Skip the warning on LED since this code isnt completed yet...
    Code (text):

    WARNING:Xst:1306 - Output <LED> is never assigned.
    WARNING:Xst:737 - Found 4-bit latch for signal <NextState>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    WARNING:Xst:2677 - Node <NextState_0> of sequential type is unconnected in block <BlinkRate>.
    WARNING:Xst:2677 - Node <NextState_1> of sequential type is unconnected in block <BlinkRate>.
    WARNING:Xst:2677 - Node <NextState_2> of sequential type is unconnected in block <BlinkRate>.
    WARNING:Xst:2677 - Node <NextState_3> of sequential type is unconnected in block <BlinkRate>.
    WARNING:Xst:2677 - Node <State_2> of sequential type is unconnected in block <BlinkRate>.
    WARNING:Xst:2677 - Node <State_1> of sequential type is unconnected in block <BlinkRate>.
    WARNING:Xst:2677 - Node <State_0> of sequential type is unconnected in block <BlinkRate>.
    WARNING:Xst:2677 - Node <State_3> of sequential type is unconnected in block <BlinProcess "Synthesize - XST" completed successfully
     
    Why is it saying it found State and NextState to be 4 bits when i create them as 2 bits?
     
    Last edited: Aug 9, 2011
  7. BrownOut

    BrownOut Banned

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    Hmmm... not sure. It might be related to the fact that you've created latches. Latches are very bad things. Like the warning says, they are created but incomplete case or if statements. For example, you code:

    Code (text):
    when "00" =>
                    if( Button = '0') then
                         NextState <= "01";
    What is the value of NextState when Button = '1'??? You haven't completely specified the assignment, so you created a latch. To fix this do this

    Code (text):
    when "00" =>
                    if( Button = '0') then
                         NextState <= "01";
                                                       else
                                                       NextState <= State;
    Or you can use a default value for NextState:


    Code (text):
        STATE_PROC:process( State,  Button)
        begin
                    Next_State <= State;
            case State is
                when "00" =>
    Maybe if you clear this up, the bits will come out right.
     
    Last edited: Aug 9, 2011
  8. AtomSoft

    AtomSoft Well-Known Member

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    Thanks yet again, i used the ELSE and was left with these warnings... (these are not errors)

    Code (text):

    WARNING:Xst:1306 - Output <LED> is never assigned.
    WARNING:Xst:2677 - Node <State_3> of sequential type is unconnected in block <BlinkRate>.
    WARNING:Xst:2677 - Node <State_2> of sequential type is unconnected in block <BlinkRate>.
    WARNING:Xst:2677 - Node <State_1> of sequential type is unconnected in block <BlinkRate>.
    WARNING:Xst:2677 - Node <State_0> of sequential type is unconnected in block <BlinkRate>.

     
    Code (text):

    ----------------------------------------------------------------------------------
    -- Company:
    -- Engineer:
    --
    -- Create Date:    16:32:16 08/08/2011
    -- Design Name:
    -- Module Name:    BlinkRate - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool versions:
    -- Description:
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity BlinkRate is
    port( Button:   in std_logic;
           Clock:       in std_logic;
           Reset:       in std_logic;
           LED:     out std_logic
    );
    end BlinkRate;

    architecture FSM of BlinkRate is
        signal Count: std_logic_vector(24 downto 0);   
        signal State: std_logic_vector(1 downto 0);
        signal NextState: std_logic_vector(1 downto 0);
    begin

       SYNC_PROC:process(Clock, Reset)
       begin   
            if ( Reset='1') then
                  State <= (others => '0');
                  Count <= (others => '0');
            elsif ( Clock'event and  Clock='1') then
                  Count <=  Count + 1;
                  State <=  NextState;
            end if;
       end process;                        
       
        STATE_PROC:process( State,  Button)
        begin
            case State is
                when "00" =>
                    if( Button = '0') then
                         NextState <= "01";
                    else
                         NextState <= "00";
                    end if;
                when "01" =>
                    if( Button = '0') then
                         NextState <= "10";
                    else
                         NextState <= "01";
                    end if;
                when "10" =>
                    if( Button = '0') then
                         NextState <= "11";
                    else
                         NextState <= "10";
                    end if;
                when "11" =>
                    if( Button = '0') then
                         NextState <= "00";
                    else
                         NextState <= "11";
                    end if;
                when others =>
                   NextState <= "00";
            end case;
        end process;   

    end FSM ;

     
     
    Last edited: Aug 9, 2011
  9. BrownOut

    BrownOut Banned

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    I think you can ignore those warnings. They say you're not using the signal "State" but you are. Is this a synthesis? What are you using?

    You'll get used to ignoring many warnings before you're done.
     
    Last edited: Aug 10, 2011
  10. AtomSoft

    AtomSoft Well-Known Member

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    yeah... take a look.. my screen...
     

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  11. BrownOut

    BrownOut Banned

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    Good job of getting the software running and creating your first designs!
     
  12. AtomSoft

    AtomSoft Well-Known Member

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    Just got my Papilio One board... looks so cool. I hand cut and soldered the headers, came out pretty good i think.
     

    Attached Files:

  13. AtomSoft

    AtomSoft Well-Known Member

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    Tested Out my Blink Led code.. the first one i ever wrote...
    Code (text):

    ----------------------------------------------------------------------------------
    -- Company:        AtomSoftTech
    -- Engineer:        Jason Lopez
    --
    -- Create Date:    09:41:51 08/01/2011
    -- Design Name:    
    -- Module Name:    BlinkLed - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool versions:
    -- Description:    Just blink LEDs
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;


    entity BlinkLed is
        Port ( LED_01 : out  STD_LOGIC;
               OSC_IN : in  STD_LOGIC;
                  RESET : in STD_LOGIC);     
    end BlinkLed;

    architecture Behavioral of BlinkLed is
        signal state : STD_LOGIC;
        signal count : STD_LOGIC_VECTOR(24 downto 0);
    begin

        process(OSC_IN, RESET) is begin
       
        if(RESET = '1') then
          state <= '0';
          count <= (others => '0');
        elsif(rising_edge(OSC_IN)) then
            if(count=16000000) then
                state <= not state;
                count <= (others => '0');
            else
                count <= count + 1;
            end if;  
        end if;
           
        end process;
       
        LED_01 <= state;

    end Behavioral;
     
    Video: (Note: RESET is pulled LOW then tied HIGH when i press the button)
     
    Last edited by a moderator: Sep 10, 2013
  14. AtomSoft

    AtomSoft Well-Known Member

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    Need some info... What would you recommend is a good protocol for getting data? Uart or spi? I like both really.
     
  15. AtomSoft

    AtomSoft Well-Known Member

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    ok new video... blinkRate change rate of blinks :)



    Code (text):

    ----------------------------------------------------------------------------------
    -- Company:
    -- Engineer:
    --
    -- Create Date:    16:32:16 08/08/2011
    -- Design Name:
    -- Module Name:    BlinkRate - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool versions:
    -- Description:
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use IEEE.numeric_std.ALL;

    entity BlinkRate is
    port( BTNA: in std_logic;
           CLOCK:   in std_logic;
           RESET:   in std_logic;
           LED:     out std_logic
    );
    end BlinkRate;

    architecture FSM of BlinkRate is
        signal Count: std_logic_vector(24 downto 0);   
        signal Rate: std_logic_vector(24 downto 0);
        signal State: std_logic_vector(1 downto 0) := "00";
        signal NXT_STATE: std_logic_vector(1 downto 0);
        signal LED_STATE : std_logic;
        --signal BTN_STATE : STD_LOGIC;
    begin

       SYNC_PROC:process(CLOCK, RESET)
       begin   
            if ( RESET='1') then
                  Count <= (others => '0');
                  LED_STATE <= '0';
            elsif ( CLOCK'event and  CLOCK='1') then
                  Count <=  Count + 1;
                  if(Count = Rate) then
                     LED_STATE <= not LED_STATE;
                     Count <= (others => '0');
                  end if;
               --State <= NXT_STATE;
            end if;
            LED <= LED_STATE;
       end process;        
       
        STATE_PROC:process(State, BTNA)
        begin
            if (  BTNA'event and BTNA='1') then
                State <= NXT_STATE;
            end if;
       
            case State is
                when "00" =>
                         Rate <= std_logic_vector( to_unsigned( 32000000, 25 ));
                         NXT_STATE <= "01";
                when "01" =>
                         Rate <= std_logic_vector( to_unsigned( 16000000, 25 ));
                         NXT_STATE <= "10";
                when "10" =>
                         Rate <= std_logic_vector( to_unsigned( 8000000, 25 ));
                         NXT_STATE <= "11";
                when "11" =>
                         Rate <= std_logic_vector( to_unsigned( 4000000, 25 ));
                         NXT_STATE <= "00";
                when others =>
                   NXT_STATE <= "00";
            end case;
        end process;   

    end FSM ;

     
     
    Last edited by a moderator: Sep 10, 2013
  16. AtomSoft

    AtomSoft Well-Known Member

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    Need some help, i tried running my shift register and noticed i want the user to be able to clock the data in instead of using a external clock.. How would i go about controlling the flow with a user generated clock?

    To clarify.... do i have to use a Global Clock Pin ? If not then how do i do this ?

    Warnings:
     
    Last edited: Aug 13, 2011
  17. AtomSoft

    AtomSoft Well-Known Member

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    Ok got it working. Here is a 16 bit shift register with CLEAR/RESET (next will be LATCH)

    Code (text):

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use IEEE.numeric_std.ALL;

    entity shift16 is
        Port ( SI : in  STD_LOGIC;
                  SC : in  STD_LOGIC;
               SR : in  STD_LOGIC;
               DB : out  STD_LOGIC_VECTOR (15 downto 0));
    end shift16;

    architecture Behavioral of shift16 is
        signal tempReg : STD_LOGIC_VECTOR (15 downto 0);
    begin

    process (SC,SR)
    begin

        if(SR = '1') then
          tempReg <= (others => '0');    
        elsif(SC'event and SC='1') then
            tempReg <= tempReg(14 downto 0) & SI;
        end if;    
       
    end process;

        DB <= tempReg;
    end Behavioral;
     
     
  18. BrownOut

    BrownOut Banned

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    UART works well if you have a serial port on your computer. I have code for a lightweight UART that I use for recreive data only.
     
  19. AtomSoft

    AtomSoft Well-Known Member

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    Yeah i think UART is a good choice. Would be simple to implement on a FPGA, But i dont want to make it auto baud just a simple 19200 bps heh... I have to order some PCBs for a project i want to do. But until then ill play around with this FPGA to see what i can come up with :)
     
  20. BrownOut

    BrownOut Banned

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    That's why I made my own. You can find details in my blog.

    BTW, in post #105 you asked:

    It dawned on my that your software is encoding your state machine "one-hot" and that's why you're getting 4 bits instead of 2. That might be default behavior of your software.
     
    Last edited: Aug 16, 2011
  21. AtomSoft

    AtomSoft Well-Known Member

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    Where is your blog? Ah, i had to look up One-Hot heh never knew about that term :)
     

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