burst mode ROM devices

[tom_electronic]

hi every body


whats burst mode Flash devise and ROM

and what is Asynchronous burst mode read access to burst mode devices ?


or what is synchronous burst mode read access to burst mode devices ?

 

[tom_electronic]

i found this but not very clear

Burst NOR FLASH
By Vas-N-Mac, Eric Mac


BURST MODE FLASH

Similarly as synchronous DRAMs migrated to more mature synchronous designs, FLASH technologies also migrated to synchronous technologies. Burst Mode FLASH uses a clock to clock out data synchronously in a burst fashion. The clock is also used to auto increment address counters inside the FLASH IC.

An example of a Burst Flash device is a Spansion device that can accept an 80 MHz clock (12.5 ns cycle time). The access time for the first word in the sequence is 80 ns. This is even slower than some asynchronous FLASH devices that operate at 70ns. But the access time for the following words in the sequence is 12.5 ns, with this 80 MHz clock. The total time required to access 16 words (32 bytes) of data is: 80 ns + (12.5 ns *15) = 267.5 ns

This yields an improvement of over 16 asynchronous accesses (80 ns * 16 = 1280 ns). In terms of average access time, a 16-word burst has an average access time of 267.5 ns/16 = 16.7 ns

Burst-mode devices allow the system to access data in 8-word, 16-word, 32-word, and continuous sequences.

SIGNALS IMPLEMENTED FOR BURST TIMING

CLK (Clock) The address and data signals are clocked on the rising edge of CLK.
CE# (Chip Enable) CE# is an active-LOW signal. When CE# is LOW the device can be accessed
by the system.
AVD# (Address Valid) AVD# is asserted LOW when the address is valid. AVD# also resets a burst
sequence.
ADR (Address) The address bus is valid when AVD# is LOW.
DQ (Data) The bi-directional data bus that can only be driven by the Flash device
when OE# is LOW.
OE# (Output Enable) OE# enables the output for read accesses.
RDY (Ready) RDY indicates that the data bus is valid. It can be programmed active-LOW
or active-HIGH. RDY is an open-drain signal to allow bussing.

FLASH BURST MODE TIMING
FLASH Burst Timing

FLASH Burst Timing

S29WS256N Flash memory device operating with an 80 MHz clock. At this frequency, the Flash device needs to be configured to insert seven wait states. RDY goes HIGH and DQ becomes valid at the seventh clock cycle. The system sets the starting address by asserting AVD# LOW. In addition, RDY becomes active when AVD# is asserted. RDY goes LOW when OE# is asserted LOW and remains LOW for the pre-programmed number of wait states. As long as RDY is LOW the data on DQ [15:0] is not valid. When RDY goes HIGH, the data word is presentedon DQ [15:0] and the internal read address is incremented on each active clock edge.

A sequence is initiated by the Address Valid signal (AVD#) going LOW and latching the starting address on either the next rising clock edge or the rising edge of AVD#. The Flash device automatically increments the address internally on each clock edge. The initial access time in a sequence is the same as the asynchronous access time (tACC). The data following initial word access is accessed on each clock edge, up to the limit of the burst access time (tBACC).

Summary

Burst Mode flash may not achieve better latency when accessing files in an embedded system. But Burst FLASH can achieve much higher thru-put bandwidth. In many embedded systems FLASH is accessed heaviest at boot up, loading the FLASH image into main memory. For applications which require faster boot up, Burst FLASH can help you achieve this goal. Also, if your design accesses the FLASH file system heavily during run time to directly access files or to load them into memory, burst FLASH can help you gain a performance advantage.


and in Spansion web page :


http://www.spansion.com/Support/AppNotes/Burst_Mode_NOR_Flash_AN_A0_E.pdf