What is a Clock period?

[Pavi98]

Hello there ,

I got a question to be answered and it says to Design a sequential logic circuit whose output will become 1 after the input remains 1 for at least 4 clock periods (Using J-K flip flops). Could you please explain about this question and help me to draw the state diagram for this circuit?

Thank You.

 

[Pommie]

It sounds like you need to design a count to four counter. You need 4 flip flops that each feed the next.

Mike.

 

[Nigel Goodwin]

A 'clock period' could be how long the battery lasts in the clock on your wall

 

[rjenkinsgb]

A clock period is the interval between two successive clock edges of the same polarity; one cycle duration, in other words.
It also implies that's a constant, fixed rate clock signal at some frequency.

Four clock cycles, for your problem.

A four stage shift register would do what you ask,; data high propogates to the final Q out in four cycles, but also use the data in low as reset for them all.
There are other ways such as counters, eg, using three J-Ks as successive divide by 2 & the third output going high also locking out the input, but the shift register is the easiest for follow.

 

[allenMark]

Hello there ,

I got a question to be answered and it says to Design a sequential logic circuit whose output will become 1 after the input remains 1 for at least 4 clock periods (Using J-K flip flops). Could you please explain about this question and help me to draw the state diagram for this circuit?

Thank You.

I think YouTube is the better source for you to understand basic JK Flip Flop

 

[danadak]

You can look at this several ways.

One way would be to collect 4 samples, using a clock edge to sample the data,
and then test the 4 samples for "1", using a shift register as rjenkinsgb mentions.
What basic gate would you use to test if 4 inputs were all "1" ?

Or set a flop and then taking one sample at a time and testing if it is a "0", if so
that flop gets cleared, otherwise its left unchanged. After 4 clocks that flop value is
transferred to a flop controlling LED. Then some logic to restart the test if this is
supposed to run continuously.

Regards, Dana.

 

[rjenkinsgb]

What basic gate would you use to test if 4 inputs were all "1" ?

You do not need to do anything but look at the output of the 4th stage, if it's done as I describe.

Using the input as /reset as well, if can only ever give a high at that point if the input is continuously high.

 

[eTech]

You do not need to do anything but look at the output of the 4th stage, if it's done as I describe.

Using the input as /reset as well, if can only ever give a high at that point if the input is continuously high.

I know what you mean, but I don't think that meets the requirement as stated(?). The 4th stage won't have been 1 for 4 periods before changing state to 1(?). Maybe I'm misinterpreting the question....

 

[eTech]

Hello there ,

I got a question to be answered and it says to Design a sequential logic circuit whose output will become 1 after the input remains 1 for at least 4 clock periods (Using J-K flip flops). Could you please explain about this question and help me to draw the state diagram for this circuit?

Thank You.

What does sequential logic tell you?
What does "for at least 4 clock periods" tell you?

What type of "JK" flip flop are you instructed to use? Do you have a manufacturer part number? or is this to be a circuit simulation?