Way to charge a capacitor linear over time

[Roff]

Jim brought up a good question: How do you want to determine the discharge rate? And why do you think it will impress the hell out of your instructor when you show him this marvel of electronics? :wink:

I gotta tell you, I'm beginning to wonder if you are taking a class in psychoelectronics. I think your assignment is to see how far you can drag some hapless design engineer (me) around by his ego. :roll:

 

[e-l-e-c-t-r-o]

Jim brought up a good question: How do you want to determine the discharge rate? And why do you think it will impress the hell out of your instructor when you show him this marvel of electronics? :wink:

I gotta tell you, I'm beginning to wonder if you are taking a class in psychoelectronics. I think your assignment is to see how far you can drag some hapless design engineer (me) around by his ego. :roll:

Many thanks JimB for the suggestion of dual slope integrator.

Found this explanation about it, and currently trying to find answers on the basis of what it says here:

**broken link removed**

Ron, of course I study psychoelectronics :lol:
My PhD thesis is: "Go to electro-tech-online, find Ron H, and them blow his brains out by stimulating his imagination on very technical, non practical, issues :roll:

No, I am just a normal student on signal processing methods, my tutor is the one to blaim since he told me to read "Practical electronics for inventors".
A good book, but after you read it makes you wanna go to places people usually don't go :roll:

Anyway, here is why I think my tutor will be impressed:

I fed into your VCO the following input (graph), deriving the output depicted.

This made me realise that the capacitor charges and then discharges due to short circuit by the 555 time (threshold exceeded etc etc).
The discharge capacitor then starts to recharge until threshold is reached again and will be discharge and then will start to charge again and SO ON.

(Right?)

This means I understood the VCO's operation.
But, I noticed that the output continues to exist even when the input reverts to zero, so i figured what if I can suggest ways to stop that?
(It will be like a "one-shot" sawtooth generator.)

If I can suggest ways to do that, and explain how these work, then NOT ONLY I comprehend the linear charging capacitors/VCOs theory, but I am able to ACT UPON those circuits.
This means expertise knowledge, imo.My tutor will be delighted, since his is into "entering bizarre electronics' field" 8)

I think my question is pretty straight forward, maybe not practical, but certainly intriguing :roll:

By the way, can you think ways of integrating into what I am asking the dual slope integrator?I think it is a good idea (but may not be needed).
Oh, not to forget to mention that the discharge rate should be fast enough to discharge the cap in time close to the charge one.Pretty simple.
We would want that in order for the whole system's process to be easily repeated.
If the discharge time is too much, then a new input signal could not be entered.

Thanks for helping out.

 

[Roff]

But, I noticed that the output continues to exist even when the input reverts to zero

When I ran the sim with zero volts on the input, the ramp output rose exponentially to 1.9V. I think the results of a sim will depend on the models you use, and actual hardware will behave somewhat differently.

So what do you actually want to do?

 

[e-l-e-c-t-r-o]

But, I noticed that the output continues to exist even when the input reverts to zero

When I ran the sim with zero volts on the input, the ramp output rose exponentially to 1.9V. I think the results of a sim will depend on the models you use, and actual hardware will behave somewhat differently.

So what do you actually want to do?

Oh,yes I noticed that difference.In my sim, the cap is charging linear.
What could likely occur in real case?

Maybe the first peak in my sim was as much as all the others.Yeap, it was, i think.

I just want to know if there is a potential for a schematic that does what the graph shows :?

In summary, various input voltages (pulse-shaped) are entered into a V-I converter, which charges a capacitor linear.
Then when the voltage across the capacitor tries to exceed the input voltage, a circuit component (DA, or 555, or dual slope integrator :?: )
"clamps" both input and output to zero; so that the system can except a signal at its initial input again. :shock:

At least let me know how much impossible that is. 8)
I was thinking of it as a "one-shot" sawtooth waveform generator.

And thank you :!:

 

[Roff]

Do you want the cap do discharge linearly (constant current), or would exponential (resistor) be OK? If you want a constant current, we will probably have to add a negative supply.
I'm assuming that the input voltage is an independent variable. What does the input voltage do when the cap voltage gets to zero? Does it stay at zero? I believe you mentioned a one-shot ramp generator. It may be easier to simply divert the charging current to GND instead of clamping the input voltage to GND.

BTW, do you have a time limit here, or can you keep fooling with it 'til the cows come home?

 

[e-l-e-c-t-r-o]

Do you want the cap do discharge linearly (constant current), or would exponential (resistor) be OK? If you want a constant current, we will probably have to add a negative supply.
I'm assuming that the input voltage is an independent variable. What does the input voltage do when the cap voltage gets to zero? Does it stay at zero? I believe you mentioned a one-shot ramp generator. It may be easier to simply divert the charging current to GND instead of clamping the input voltage to GND.

BTW, do you have a time limit here, or can you keep fooling with it 'til the cows come home?

Hi, I am back! (A lot of study for the past two days) :?

Ok, here is a graph from my sim when I feed the input into the VCO.

As you can see, no input works as what I think we can come up with. :cry:

While reading the dual slope integrator, I came up with the perception that a DSI could be used in conjuction with the V-I converter you designed.

I searched into the internet for a DSI and found these two:

**broken link removed**

**broken link removed**

Could they be of any use (at least I could use that to propose to my tutor the base-theory of what I could do to make my idea come true :roll: )

Still, I don't have the theory base (the main idea) :cry:

My assignment is due in a few days .So I am kinda in a hurry

Now, about your questions.

It could be nice for the capacitor to discharge linearly.I don't mind with the dual supply.Unless there could be a drawback there. :roll:

The whole concept of "forcing" the input to revert to zero is for the whole system to be able to "except" an input signal again (especially smaller ones).Considering this condition to be met, can you find the appropriate answer :?:
IMO, the input's "clamp" should occur only at one condition, when the capacitor's voltage tries to exceed the input voltage level (at any given time, during variable input voltages ).
Any time that capacitor voltage is less than the input voltage, there is not clamp to the input voltage. :shock:

I shall answer your last technical question in another post (need to depict the answer in a new graph :roll:

 

[e-l-e-c-t-r-o]

See this graph.

It is the output I want to have as time evolves and as input voltages change in level as well as when "time of voltage level change" changes. 8)

Fuels into imagination deposit, 3, 2, 1, GO!!! :!:

Help appreciated.

 

[Roff]

The trouble with the dual slope integrator is that, IMHO, you dont have time to do it. It requires counters and logic (or something like a PIC) to implement it. And an op amp integrator is a MUCH better way to do it. See **broken link removed**.
Regarding your last post - If you clamp the input voltage to zero, what is going to cause that clamp to be released? Are you going to do it with a mechanical (pushbutton) switch, or does it release after a fixed period of time, or... :?:

 

[e-l-e-c-t-r-o]

The trouble with the dual slope integrator is that, IMHO, you dont have time to do it. It requires counters and logic (or something like a PIC) to implement it. And an op amp integrator is a MUCH better way to do it. See **broken link removed**.
Regarding your last post - If you clamp the input voltage to zero, what is going to cause that clamp to be released? Are you going to do it with a mechanical (pushbutton) switch, or does it release after a fixed period of time, or... :?:

As the graph indicates, the clamp-release occures after "change of condition between in/out voltage levels".

You can see that the clamp condition starts when the output (capacitor voltage) gets greater than input voltage.
The clampl of both in/out occurs until the point where the output becomes less than the input.
Of course, that operation requires the input voltage to be clamped much more drastically than the output 8)

Is that possible? :roll:

 

[Roff]

The trouble with the dual slope integrator is that, IMHO, you dont have time to do it. It requires counters and logic (or something like a PIC) to implement it. And an op amp integrator is a MUCH better way to do it. See **broken link removed**.
Regarding your last post - If you clamp the input voltage to zero, what is going to cause that clamp to be released? Are you going to do it with a mechanical (pushbutton) switch, or does it release after a fixed period of time, or... :?:

As the graph indicates, the clamp-release occures after "change of condition between in/out voltage levels".

You can see that the clamp condition starts when the output (capacitor voltage) gets greater than input voltage.
The clampl of both in/out occurs until the point where the output becomes less than the input.
Of course, that operation requires the input voltage to be clamped much more drastically than the output 8)

Is that possible? :roll:

I don't think you understand my question. Where does your input voltage come from? When the input voltage gets clamped, it doesn't go away, like the charge on the cap does when it gets discharged. The input voltage is still there - it is just "disconnected" from the input. If you release the input clamp as soon as the cap discharges, the cap will start to charge again. Then you have an oscillator, as we have discussed. If, on the other hand, you latch the input clamp, you will need some sort of external stimulus to reset the clamp.
I think the key point I'm trying to make is that the input voltage is (in my mind) an independent control voltage. If it goes to zero when you clamp it, how does it assume a non-zero value some finite length of time later?

 

[e-l-e-c-t-r-o]

The trouble with the dual slope integrator is that, IMHO, you dont have time to do it. It requires counters and logic (or something like a PIC) to implement it. And an op amp integrator is a MUCH better way to do it. See **broken link removed**.
Regarding your last post - If you clamp the input voltage to zero, what is going to cause that clamp to be released? Are you going to do it with a mechanical (pushbutton) switch, or does it release after a fixed period of time, or... :?:

As the graph indicates, the clamp-release occures after "change of condition between in/out voltage levels".

You can see that the clamp condition starts when the output (capacitor voltage) gets greater than input voltage.
The clampl of both in/out occurs until the point where the output becomes less than the input.
Of course, that operation requires the input voltage to be clamped much more drastically than the output 8)

Is that possible? :roll:

I don't think you understand my question. Where does your input voltage come from? When the input voltage gets clamped, it doesn't go away, like the charge on the cap does when it gets discharged. The input voltage is still there - it is just "disconnected" from the input. If you release the input clamp as soon as the cap discharges, the cap will start to charge again. Then you have an oscillator, as we have discussed. If, on the other hand, you latch the input clamp, you will need some sort of external stimulus to reset the clamp.
I think the key point I'm trying to make is that the input voltage is (in my mind) an independent control voltage. If it goes to zero when you clamp it, how does it assume a non-zero value some finite length of time later?

Oh, let me see if I got your question :?

The input signal I designed in the graph we can assume to occur due to another signal before it.
Meaning, that dc voltage variation could come from a signal before it that has a fixed time of occurence (this is why I reffered to the system as "one-shot"); let's say 15ms.
For example, it may be an analog sine wave. :shock:

The sine wave could have different peak levels that are converted into relative DC signals (not same levels' conversion-just relative; But I don't know if that is possible ).

So, the real problem would be that the DC converted signal has infinite time of occurence, while the signal before it has a finite time (15ms).

In addition, a second finite sine wave can occur only after 30ms from the first (we set this as a "rule of thump", cause it simplifies the way the clamp could be released).

Considering all the above, I think the simplest (if not the only) way to go is by setting a fixed time period for the external stimulus to reset the clamp.

Assuming the input signal takes its maximum level in no more than 15ms, then the capacitor discharges around the 25th millisecond. :idea:

So, the input can be stopped to be clamped after the 26st millisecond 8)
The circuit could understand IF & WHEN an input clamp has occured, and release the clamp after a fixed period of time.

(The trick in such operation success is a "rule of thump" we can set:
That the input lasts for 15ms, and another input signal can occur only after 30 ms from the first one. 8) )

Now, the big question is of course HOW that can be done :roll:

Despite of designing the exact operation, which I am sure you can do far better than me,
I think another base in deciding not to reset the clamp while the capacitor is discharging could be the one I mentioned in my previous post:
the circuit's ability to compare the input/output levels, and be aware when the one becomes greater than the other. :shock:

In plain English, the circuit should understand that an input clamp has occured, and decide not to release that clamped until the output level becomes less than input one.

Summary: The whole concept is that a "one-shot" input occurs (i.e a sine wave), convert its peak fluctuations into (relative) DC level fluctuations, then charge a capacitor linear to produce a "one-shot" sawtooth waveform, while clamping both DC level and capacitor voltage so that a second "one-shot sine wave" can occur after a certain before of time from the first. 8)

 

[Roff]

That's too complicated. I'm still not really understanding you. I don't have time to figure out what you want and then design it.

 

[e-l-e-c-t-r-o]

That's too complicated. I'm still not really understanding you. I don't have time to figure out what you want and then design it.

:cry:

Ron H, I have given som thought and made it pretty straightforward.

Here is a graph with all the stages.

The stages are:

1. An- of "random occurence"/"random voltage level" Signal (Any kind of random sine or triangle wave, i.e a sound)

2. The signal is fed into a circuit that transforms its "corners" into DC levels.
(Unfortunately I don't know how to do that Maybe it can be done with some kind of rectification :roll: )

3. The DC level signal goes into a V-I converter that charges a capacitor linearly.

NOW, the problem here is that due to the step 2 process, the first input greats a DC voltage output that lasts FOREVER (Remember that!)

The next input cannot be inserted unless there is some kind of "input disconnect" from the circuit.

The same applies for the linear charging capacitor!

The cap charges up to the V-I operational point.

The system looses a vital info about the differences of maximum voltage level between different inputs in stage 1 :roll:

4. The linear charging capacitor is discharged when the dc voltage (input to the V-I) is equal with the voltage across the cap.
In addition, the DC voltage (input) is also clamped to zero as long as the (decreasing) cap voltage is greater than the clamped DC;
OR
for a fixed time set by us, preferably 25-30ms after the time point where the voltage clamp started. 8)

Here is the graph.
Thanks for helping out :lol:

 

[e-l-e-c-t-r-o]

At least someone here to suggest a theory frame?

Like a block diagram or something. :roll:

Great thanks for the help. :wink:

 

[Roff]

See if this will work for you. It works in simulation with a DC control voltage. I had to set an initial condition for the voltage on the ramp cap (.IC v(cap)=0). Otherwise, it didn't run as a VCO.
The input voltage isn't clamped. Instead, I cut off the current in the first VCCS (R11, D5, D6). It should work better than a clamp.
See if you can figure out how it all works.

My problem is, this has gotten so complex that it is no longer trivial. I actually have to spend time designing, and I'm pressed for time.

 

[e-l-e-c-t-r-o]

I must admit your help has been more than enough

A BIG thank you, man, you deserve it! 8)

Considering you have designed a schematic, may I put you into trouble in asking you to declare a LITTLE general theory into the schematic?

You see, I have been trying today to simulate it, I haven't been able to do so, I am afraid :roll:

The signal I am getting across the cap is linear, greater slope for greater voltage, but the cap does not discharge (in my sim)

I understood the parts that are described on the schematic (those included in dotted boxes), however I cannot manage to comprehent the other parts.

For instance, I read about flip-flops too, but I could not see how that helps for the capacitor to discharge and for the initial input to be "disconnected" from the circuit.

A block diagram with all the steps/stages and a title for its stage is all I am asking, I think :roll:
And if it is easy, could you please put into your simulation the 3 different inputs depicted in the graph below?
I think the best way for me to understand if the circuit does what I thought it could do is to see the in/out graphs.

Many thanks, again.
Sorry if I spoiled your precious time.
:roll:
Well, I think you have helped in forming me into a better circuit designer :!: (if I am at all that )

 

[Roff]

I made one error in the schematic. It works as I drew it, but I'm posting a new schematic with the inverting input of U5 connected to C1 instead of ramp, which is the buffered output. It will be easier to describe the operation with this change.

I also realized that it would probably be better to connect the output of U3 to the PRESET input of A1, and tie the CLK input to GND. This should prevent the potential lockup condition which can occur, at least in the sim, and maybe in hardware. I solved it in the sim by setting .IC v(cap)=0. I didn't make this change on the new schematic.

I can't sim this now, because the file is in my computer at work, and I'm at home. I'll try to describe how it works.

You already know how the VCCS, the current mirror and the voltage follower work.

Q6 and R12, when Q6 is on (it is initially off), provide the current sink which will discharge C1 linearly. U3 is a comparator that senses when the ramp exceeds the control voltage. When this occurs, U3's output rises abruptly (guaranteed by the slight amount of positive feedback through R6), clocking a logic "1" (vcc on the D input) into A1 and causing A1Q to go high (vcc) and Q/ to go low (0V). This forces about a milliamp through D5 and D6, cutting off Q1, which in turn shuts off the current into C1 (this is equivalent to clamping the control voltage to zero, but is easier). At the same time, current ceases to flow through D3 and D4 (Q/ had been high and is now low), so Q6 turns on, discharging C1 with a current of about (9-0.7)/82k=100uA. C1 voltage slopes in a negative direction until U5 senses that it has gotten to GND (which is on the + input pin). When this happens, U5 output goes positive by 2 diode drops (approx +1.2V), clamping C1 to zero volts by diverting the discharge current, which was flowing through C1, through D1 and D2. With 1.2V on the U5 output, Q3 turns on, which turns off Q4. This applies vcc to the CLR input to A1, causing the outputs to switch states. This turns off the discharge current sink Q6 and simultaneously enables Q1 once again (by cutting off D5). If a non-zero control voltage is present, C1 will begin to charge again. If the control voltage has gone to zero (as you showed in a previous post), C1 will float, and may slowly charge due to U1 and U2 offset voltages and U4 input bias current (it can't discharge further, because U5 prevents it). Floating is not desirable, but it is one of the scenarios you proposed.

I hope this makes sense. I'm gonna be out of town for the rest of the week, starting around noon tomorrow.

 

[e-l-e-c-t-r-o]

I made one error in the schematic. It works as I drew it, but I'm posting a new schematic with the inverting input of U5 connected to C1 instead of ramp, which is the buffered output. It will be easier to describe the operation with this change.

I also realized that it would probably be better to connect the output of U3 to the PRESET input of A1, and tie the CLK input to GND. This should prevent the potential lockup condition which can occur, at least in the sim, and maybe in hardware. I solved it in the sim by setting .IC v(cap)=0. I didn't make this change on the new schematic.

I can't sim this now, because the file is in my computer at work, and I'm at home. I'll try to describe how it works.

You already know how the VCCS, the current mirror and the voltage follower work.

Q6 and R12, when Q6 is on (it is initially off), provide the current sink which will discharge C1 linearly. U3 is a comparator that senses when the ramp exceeds the control voltage. When this occurs, U3's output rises abruptly (guaranteed by the slight amount of positive feedback through R6), clocking a logic "1" (vcc on the D input) into A1 and causing A1Q to go high (vcc) and Q/ to go low (0V). This forces about a milliamp through D5 and D6, cutting off Q1, which in turn shuts off the current into C1 (this is equivalent to clamping the control voltage to zero, but is easier). At the same time, current ceases to flow through D3 and D4 (Q/ had been high and is now low), so Q6 turns on, discharging C1 with a current of about (9-0.7)/82k=100uA. C1 voltage slopes in a negative direction until U5 senses that it has gotten to GND (which is on the + input pin). When this happens, U5 output goes positive by 2 diode drops (approx +1.2V), clamping C1 to zero volts by diverting the discharge current, which was flowing through C1, through D1 and D2. With 1.2V on the U5 output, Q3 turns on, which turns off Q4. This applies vcc to the CLR input to A1, causing the outputs to switch states. This turns off the discharge current sink Q6 and simultaneously enables Q1 once again (by cutting off D5). If a non-zero control voltage is present, C1 will begin to charge again. If the control voltage has gone to zero (as you showed in a previous post), C1 will float, and may slowly charge due to U1 and U2 offset voltages and U4 input bias current (it can't discharge further, because U5 prevents it). Floating is not desirable, but it is one of the scenarios you proposed.

I hope this makes sense. I'm gonna be out of town for the rest of the week, starting around noon tomorrow.

I'll take it home, sim it, study it a little bit, and let u know today. :lol:

Nice theory explanation. 8)

The only thing I did not quite get is the "floating" thing at the end :roll:

I am a little concerned about the "non-control voltage" state. :?:

That thing about the slow charge of the capacitor. :?
I think it should not be there :roll: Can you explain a little bit?

Last but not least, would you mind putting the different control voltages into your sim, at some point of time before you leave?

It would be vital to have in/out graphs of a "working circuit"; since I did not manage to make mine work and yours is, what about you simulating it?

Thank you.Best circuit designer I 'd ever thought I could discuss with. 8)

 

[Roff]

I changed the connection from U3 output to A1 PRE, as discussed above. I ran the sim for two different input scenarios, as shown. If you need more, you'll have to figure out how to run the sim.
With zero control voltage, the ramp actually oscillates between ~+18mV and -18mV (this occurs during the time I predicted the "float". I was wrong. ). The control loop tries to keep it at zero, but propagation delay around the control loop makes it oscillate. This could be minimized by using faster transistors (Q3 and Q4), faster op amps (U4 and U5), a faster comparator (U3), and a faster flip-flop (A1). Using a faster Q6 would be of little help, because it doesn't saturate (no storage time).
Various other schemes could be devised to speed up the loop, but I think it is impossible to totally eliminate the oscillation, due to the digital device (A1) in the loop.

 

[e-l-e-c-t-r-o]

I changed the connection from U3 output to A1 PRE, as discussed above. I ran the sim for two different input scenarios, as shown. If you need more, you'll have to figure out how to run the sim.
With zero control voltage, the ramp actually oscillates between ~+18mV and -18mV (this occurs during the time I predicted the "float". I was wrong. ). The control loop tries to keep it at zero, but propagation delay around the control loop makes it oscillate. This could be minimized by using faster transistors (Q3 and Q4), faster op amps (U4 and U5), a faster comparator (U3), and a faster flip-flop (A1). Using a faster Q6 would be of little help, because it doesn't saturate (no storage time).
Various other schemes could be devised to speed up the loop, but I think it is impossible to totally eliminate the oscillation, due to the digital device (A1) in the loop.

I think the oscillation is too little to cause trouble. :?

I have been simulating too, in my sim something is not working, but I bet I'll find it :wink:

Now, since in yours it works, I have the theory background, the schematics, so the A+ is in my pocket.
I'll put you all into my reference list
Especially Ron H 8)

With bold letters!

Anyway, one last question:

The input (control voltage), do you (by default) insert it into the circuit to "go to zero after the 5th ms", OR
the circuit does that (revert input to zero)?

I am assuming the circuit does it.

So this means everything is as I thought they could be.

Maybe I 'll spend a couple of spare weekends (maybe it takes more) building that darn thing :!:

Do you by any chance can think of potential "problems" in reality that are not depicted into sim?
Like things I should expect to might not work, or to behave unstable, or even different.
Experience matters, I think, in analog circuit world.
Would be cool to share yours with us, imo :roll:

Thank you so very much.I hope one day I can design circuits like that. :wink: