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VHDL Full adder 4-bit

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diamadiss

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Hi to everyone. I want to help me someone to make work a parallel full adder. I make the scematic i program Xilinx9.1, and i have that problem. If i have carry(C0Cin) '1' it works OK, but if i have a carry '0' doesen't true add and the childe is wrong. I think tha i connect wrong, because programe now i learn it. Thanks for patient.

The scematic i upload it here :
Send big files the easy way. Files too large for email attachments? No problem!

Code:
http://www.sendspace.com/file/eowqgn
 
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